From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1725) id 1DA9C3858D20; Fri, 4 Feb 2022 19:32:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1DA9C3858D20 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: William Schmidt To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-7060] rs6000: Clean up ISA 3.1 documentation [PR100808] X-Act-Checkin: gcc X-Git-Author: Bill Schmidt X-Git-Refname: refs/heads/master X-Git-Oldrev: 8d6fffc4bcd4afa0beb0efad4f3b95394aa15618 X-Git-Newrev: 8cb748a31cd8c7ac9c88b6abc38ce077dd462a7a Message-Id: <20220204193217.1DA9C3858D20@sourceware.org> Date: Fri, 4 Feb 2022 19:32:17 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Feb 2022 19:32:17 -0000 https://gcc.gnu.org/g:8cb748a31cd8c7ac9c88b6abc38ce077dd462a7a commit r12-7060-g8cb748a31cd8c7ac9c88b6abc38ce077dd462a7a Author: Bill Schmidt Date: Fri Feb 4 13:26:44 2022 -0600 rs6000: Clean up ISA 3.1 documentation [PR100808] Due to a pasto error in the documentation, vec_replace_unaligned was implemented with the same function prototypes as vec_replace_elt. It was intended that vec_replace_unaligned always specify output vectors as having type vector unsigned char, to emphasize that elements are potentially misaligned by this built-in function. This patch corrects the misimplementation. 2022-02-04 Bill Schmidt gcc/ PR target/100808 * doc/extend.texi (Basic PowerPC Built-in Functions Available on ISA 3.1): Provide consistent type names. Remove unnecessary semicolons. Fix bad line breaks. Diff: --- gcc/doc/extend.texi | 71 ++++++++++++++++++++++++++++++++--------------------- 1 file changed, 43 insertions(+), 28 deletions(-) diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index a961fc4e0a2..cb1b2b98ca8 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -18276,74 +18276,89 @@ The following built-in functions are available on Linux 64-bit systems that use a future architecture instruction set (@option{-mcpu=power10}): @smallexample -@exdent unsigned long long int -@exdent __builtin_cfuged (unsigned long long int, unsigned long long int) +@exdent unsigned long long +@exdent __builtin_cfuged (unsigned long long, unsigned long long) @end smallexample Perform a 64-bit centrifuge operation, as if implemented by the @code{cfuged} instruction. @findex __builtin_cfuged @smallexample -@exdent unsigned long long int -@exdent __builtin_cntlzdm (unsigned long long int, unsigned long long int) +@exdent unsigned long long +@exdent __builtin_cntlzdm (unsigned long long, unsigned long long) @end smallexample Perform a 64-bit count leading zeros operation under mask, as if implemented by the @code{cntlzdm} instruction. @findex __builtin_cntlzdm @smallexample -@exdent unsigned long long int -@exdent __builtin_cnttzdm (unsigned long long int, unsigned long long int) +@exdent unsigned long long +@exdent __builtin_cnttzdm (unsigned long long, unsigned long long) @end smallexample Perform a 64-bit count trailing zeros operation under mask, as if implemented by the @code{cnttzdm} instruction. @findex __builtin_cnttzdm @smallexample -@exdent unsigned long long int -@exdent __builtin_pdepd (unsigned long long int, unsigned long long int) +@exdent unsigned long long +@exdent __builtin_pdepd (unsigned long long, unsigned long long) @end smallexample Perform a 64-bit parallel bits deposit operation, as if implemented by the @code{pdepd} instruction. @findex __builtin_pdepd @smallexample -@exdent unsigned long long int -@exdent __builtin_pextd (unsigned long long int, unsigned long long int) +@exdent unsigned long long +@exdent __builtin_pextd (unsigned long long, unsigned long long) @end smallexample Perform a 64-bit parallel bits extract operation, as if implemented by the @code{pextd} instruction. @findex __builtin_pextd @smallexample -@exdent vector signed __int128 vsx_xl_sext (signed long long, signed char *); -@exdent vector signed __int128 vsx_xl_sext (signed long long, signed short *); -@exdent vector signed __int128 vsx_xl_sext (signed long long, signed int *); -@exdent vector signed __int128 vsx_xl_sext (signed long long, signed long long *); -@exdent vector unsigned __int128 vsx_xl_zext (signed long long, unsigned char *); -@exdent vector unsigned __int128 vsx_xl_zext (signed long long, unsigned short *); -@exdent vector unsigned __int128 vsx_xl_zext (signed long long, unsigned int *); -@exdent vector unsigned __int128 vsx_xl_zext (signed long long, unsigned long long *); +@exdent vector signed __int128 vsx_xl_sext (signed long long, signed char *) + +@exdent vector signed __int128 vsx_xl_sext (signed long long, signed short *) + +@exdent vector signed __int128 vsx_xl_sext (signed long long, signed int *) + +@exdent vector signed __int128 vsx_xl_sext (signed long long, signed long long *) + +@exdent vector unsigned __int128 vsx_xl_zext (signed long long, unsigned char *) + +@exdent vector unsigned __int128 vsx_xl_zext (signed long long, unsigned short *) + +@exdent vector unsigned __int128 vsx_xl_zext (signed long long, unsigned int *) + +@exdent vector unsigned __int128 vsx_xl_zext (signed long long, unsigned long long *) @end smallexample Load (and sign extend) to an __int128 vector, as if implemented by the ISA 3.1 -@code{lxvrbx} @code{lxvrhx} @code{lxvrwx} @code{lxvrdx} instructions. +@code{lxvrbx}, @code{lxvrhx}, @code{lxvrwx}, and @code{lxvrdx} instructions. @findex vsx_xl_sext @findex vsx_xl_zext @smallexample -@exdent void vec_xst_trunc (vector signed __int128, signed long long, signed char *); -@exdent void vec_xst_trunc (vector signed __int128, signed long long, signed short *); -@exdent void vec_xst_trunc (vector signed __int128, signed long long, signed int *); -@exdent void vec_xst_trunc (vector signed __int128, signed long long, signed long long *); -@exdent void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *); -@exdent void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned short *); -@exdent void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned int *); -@exdent void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned long long *); +@exdent void vec_xst_trunc (vector signed __int128, signed long long, signed char *) + +@exdent void vec_xst_trunc (vector signed __int128, signed long long, signed short *) + +@exdent void vec_xst_trunc (vector signed __int128, signed long long, signed int *) + +@exdent void vec_xst_trunc (vector signed __int128, signed long long, signed long long *) + +@exdent void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned char *) + +@exdent void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned short *) + +@exdent void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned int *) + +@exdent void vec_xst_trunc (vector unsigned __int128, signed long long, unsigned long long *) @end smallexample Truncate and store the rightmost element of a vector, as if implemented by the -ISA 3.1 @code{stxvrbx} @code{stxvrhx} @code{stxvrwx} @code{stxvrdx} instructions. +ISA 3.1 @code{stxvrbx}, @code{stxvrhx}, @code{stxvrwx}, and @code{stxvrdx} +instructions. @findex vec_xst_trunc @node PowerPC AltiVec/VSX Built-in Functions