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From: Kewen Lin <linkw@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-7078] rs6000: Disable MMA if no VSX support [PR103627] Date: Mon, 7 Feb 2022 05:48:49 +0000 (GMT) [thread overview] Message-ID: <20220207054849.953EA3858C83@sourceware.org> (raw) https://gcc.gnu.org/g:8103623923ac4ea19b97a369979d4bd5731aab57 commit r12-7078-g8103623923ac4ea19b97a369979d4bd5731aab57 Author: Kewen Lin <linkw@linux.ibm.com> Date: Sun Feb 6 21:29:32 2022 -0600 rs6000: Disable MMA if no VSX support [PR103627] As PR103627 shows, there is an unexpected case where !TARGET_VSX and TARGET_MMA co-exist. As ISA3.1 claims, SIMD is a requirement for MMA. By looking into the ICE, I noticed that the current MMA implementation depends on vector pairs load/store which use VSX register, but we don't have a separated option to control Power10 vector support and Segher pointed out "-mpower9-vector is a workaround that should go away" and more explanations in [1]. So this patch makes MMA require VSX instead. [1] https://gcc.gnu.org/pipermail/gcc-patches/2022-January/589303.html gcc/ChangeLog: PR target/103627 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Disable MMA if !TARGET_VSX. gcc/testsuite/ChangeLog: PR target/103627 * gcc.target/powerpc/pr103627-1.c: New test. * gcc.target/powerpc/pr103627-2.c: New test. Diff: --- gcc/config/rs6000/rs6000.cc | 10 ++++++++++ gcc/testsuite/gcc.target/powerpc/pr103627-1.c | 16 ++++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr103627-2.c | 16 ++++++++++++++++ 3 files changed, 42 insertions(+) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index d9fc67d5d29..a2843d1caef 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4482,6 +4482,16 @@ rs6000_option_override_internal (bool global_init_p) rs6000_isa_flags &= ~OPTION_MASK_MMA; } + /* MMA requires SIMD support as ISA 3.1 claims and our implementation + such as "*movoo" uses vector pair access which use VSX registers. + So make MMA require VSX support here. */ + if (TARGET_MMA && !TARGET_VSX) + { + if ((rs6000_isa_flags_explicit & OPTION_MASK_MMA) != 0) + error ("%qs requires %qs", "-mmma", "-mvsx"); + rs6000_isa_flags &= ~OPTION_MASK_MMA; + } + if (!TARGET_PCREL && TARGET_PCREL_OPT) rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT; diff --git a/gcc/testsuite/gcc.target/powerpc/pr103627-1.c b/gcc/testsuite/gcc.target/powerpc/pr103627-1.c new file mode 100644 index 00000000000..5cecf515e58 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr103627-1.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -mno-vsx" } */ + +/* Verify compiler emits error message instead of ICE. */ + +extern float *dest; +extern __vector_quad src; + +int +foo () +{ + __builtin_mma_disassemble_acc (dest, &src); + /* { dg-error "'__builtin_mma_disassemble_acc' requires the '-mmma' option" "" { target *-*-* } .-1 } */ + return 0; +} + diff --git a/gcc/testsuite/gcc.target/powerpc/pr103627-2.c b/gcc/testsuite/gcc.target/powerpc/pr103627-2.c new file mode 100644 index 00000000000..89ae4f607bf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr103627-2.c @@ -0,0 +1,16 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -mmma -mno-vsx" } */ + +/* Verify the emitted error message. */ + +extern float *dest; +extern __vector_quad src; + +int +foo () +{ + __builtin_mma_disassemble_acc (dest, &src); + /* { dg-error "'-mmma' requires '-mvsx'" "mma" { target *-*-* } 0 } */ + return 0; +} +
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