From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id F3D043858431; Wed, 9 Feb 2022 16:57:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F3D043858431 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Richard Sandiford To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-7138] aarch64: Remove redundant vec_concat patterns X-Act-Checkin: gcc X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/trunk X-Git-Oldrev: 958448a9441ee54e012c67cfc3cf88083f3d0e4a X-Git-Newrev: aeef5c57f161ad0258c5ab066ade2274bef3271a Message-Id: <20220209165736.F3D043858431@sourceware.org> Date: Wed, 9 Feb 2022 16:57:36 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Feb 2022 16:57:37 -0000 https://gcc.gnu.org/g:aeef5c57f161ad0258c5ab066ade2274bef3271a commit r12-7138-gaeef5c57f161ad0258c5ab066ade2274bef3271a Author: Richard Sandiford Date: Wed Feb 9 16:57:04 2022 +0000 aarch64: Remove redundant vec_concat patterns move_lo_quad_internal_ and move_lo_quad_internal_be_ partially duplicate the later aarch64_combinez{,_be} patterns. The duplication itself is a regression. The only substantive differences between the two are: * combinez uses vector MOV (ORR) instead of element MOV (DUP). The former seems more likely to be handled via renaming. * combinez disparages the GPR->FPR alternative whereas move_lo_quad gave it equal cost. The new test gives a token example of when the combinez behaviour helps. gcc/ * config/aarch64/aarch64-simd.md (move_lo_quad_internal_) (move_lo_quad_internal_be_): Delete. (move_lo_quad_): Use aarch64_combine instead of the above. gcc/testsuite/ * gcc.target/aarch64/vec-init-8.c: New test. Diff: --- gcc/config/aarch64/aarch64-simd.md | 37 ++------------------------- gcc/testsuite/gcc.target/aarch64/vec-init-8.c | 15 +++++++++++ 2 files changed, 17 insertions(+), 35 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index c5bc2ea658b..d6cd4c70fe7 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1584,46 +1584,13 @@ ;; On little-endian this is { operand, zeroes } ;; On big-endian this is { zeroes, operand } -(define_insn "move_lo_quad_internal_" - [(set (match_operand:VQMOV 0 "register_operand" "=w,w,w") - (vec_concat:VQMOV - (match_operand: 1 "register_operand" "w,r,r") - (match_operand: 2 "aarch64_simd_or_scalar_imm_zero")))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "@ - dup\\t%d0, %1.d[0] - fmov\\t%d0, %1 - dup\\t%d0, %1" - [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "length" "4") - (set_attr "arch" "simd,fp,simd")] -) - -(define_insn "move_lo_quad_internal_be_" - [(set (match_operand:VQMOV 0 "register_operand" "=w,w,w") - (vec_concat:VQMOV - (match_operand: 2 "aarch64_simd_or_scalar_imm_zero") - (match_operand: 1 "register_operand" "w,r,r")))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" - "@ - dup\\t%d0, %1.d[0] - fmov\\t%d0, %1 - dup\\t%d0, %1" - [(set_attr "type" "neon_dup,f_mcr,neon_dup") - (set_attr "length" "4") - (set_attr "arch" "simd,fp,simd")] -) - (define_expand "move_lo_quad_" [(match_operand:VQMOV 0 "register_operand") (match_operand: 1 "register_operand")] "TARGET_SIMD" { - rtx zs = CONST0_RTX (mode); - if (BYTES_BIG_ENDIAN) - emit_insn (gen_move_lo_quad_internal_be_ (operands[0], operands[1], zs)); - else - emit_insn (gen_move_lo_quad_internal_ (operands[0], operands[1], zs)); + emit_insn (gen_aarch64_combine (operands[0], operands[1], + CONST0_RTX (mode))); DONE; } ) diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-8.c b/gcc/testsuite/gcc.target/aarch64/vec-init-8.c new file mode 100644 index 00000000000..18f8afe10f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-8.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#include + +int64x2_t f1(int64_t *ptr) { + int64_t x = *ptr; + asm volatile ("" ::: "memory"); + if (__BYTE_ORDER__ == __ORDER_BIG_ENDIAN__) + return (int64x2_t) { 0, x }; + else + return (int64x2_t) { x, 0 }; +} + +/* { dg-final { scan-assembler {\tldr\td0, \[x0\]\n} } } */