From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1130) id 53EE2385842C; Wed, 9 Feb 2022 16:57:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 53EE2385842C MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Richard Sandiford To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-7141] aarch64: Remove move_lo/hi_quad expanders X-Act-Checkin: gcc X-Git-Author: Richard Sandiford X-Git-Refname: refs/heads/trunk X-Git-Oldrev: 4057266ce5afc1fccd5d4e4971103afaa4be63d4 X-Git-Newrev: bce43c0493f65d2589776f0dafa396d5477a84c7 Message-Id: <20220209165752.53EE2385842C@sourceware.org> Date: Wed, 9 Feb 2022 16:57:52 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Feb 2022 16:57:52 -0000 https://gcc.gnu.org/g:bce43c0493f65d2589776f0dafa396d5477a84c7 commit r12-7141-gbce43c0493f65d2589776f0dafa396d5477a84c7 Author: Richard Sandiford Date: Wed Feb 9 16:57:06 2022 +0000 aarch64: Remove move_lo/hi_quad expanders This patch is the second of two to remove the old move_lo/hi_quad expanders and move_hi_quad insns. gcc/ * config/aarch64/aarch64-simd.md (@aarch64_split_simd_mov): Use aarch64_combine instead of move_lo/hi_quad. Tabify. (move_lo_quad_, aarch64_simd_move_hi_quad_): Delete. (aarch64_simd_move_hi_quad_be_, move_hi_quad_): Delete. (vec_pack_trunc_): Take general_operand elements and use aarch64_combine rather than move_lo/hi_quad to combine them. (vec_pack_trunc_df): Likewise. Diff: --- gcc/config/aarch64/aarch64-simd.md | 111 ++++++------------------------------- 1 file changed, 18 insertions(+), 93 deletions(-) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 7acde0dd099..ef6e772503d 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -272,7 +272,7 @@ (define_expand "@aarch64_split_simd_mov" [(set (match_operand:VQMOV 0) - (match_operand:VQMOV 1))] + (match_operand:VQMOV 1))] "TARGET_SIMD" { rtx dst = operands[0]; @@ -280,23 +280,22 @@ if (GP_REGNUM_P (REGNO (src))) { - rtx src_low_part = gen_lowpart (mode, src); - rtx src_high_part = gen_highpart (mode, src); + rtx src_low_part = gen_lowpart (mode, src); + rtx src_high_part = gen_highpart (mode, src); + rtx dst_low_part = gen_lowpart (mode, dst); - emit_insn - (gen_move_lo_quad_ (dst, src_low_part)); - emit_insn - (gen_move_hi_quad_ (dst, src_high_part)); + emit_move_insn (dst_low_part, src_low_part); + emit_insn (gen_aarch64_combine (dst, dst_low_part, + src_high_part)); } - else { - rtx dst_low_part = gen_lowpart (mode, dst); - rtx dst_high_part = gen_highpart (mode, dst); + rtx dst_low_part = gen_lowpart (mode, dst); + rtx dst_high_part = gen_highpart (mode, dst); rtx lo = aarch64_simd_vect_par_cnst_half (mode, , false); rtx hi = aarch64_simd_vect_par_cnst_half (mode, , true); - emit_insn (gen_aarch64_get_half (dst_low_part, src, lo)); - emit_insn (gen_aarch64_get_half (dst_high_part, src, hi)); + emit_insn (gen_aarch64_get_half (dst_low_part, src, lo)); + emit_insn (gen_aarch64_get_half (dst_high_part, src, hi)); } DONE; } @@ -1580,69 +1579,6 @@ ;; What that means, is that the RTL descriptions of the below patterns ;; need to change depending on endianness. -;; Move to the low architectural bits of the register. -;; On little-endian this is { operand, zeroes } -;; On big-endian this is { zeroes, operand } - -(define_expand "move_lo_quad_" - [(match_operand:VQMOV 0 "register_operand") - (match_operand: 1 "register_operand")] - "TARGET_SIMD" -{ - emit_insn (gen_aarch64_combine (operands[0], operands[1], - CONST0_RTX (mode))); - DONE; -} -) - -;; Move operand1 to the high architectural bits of the register, keeping -;; the low architectural bits of operand2. -;; For little-endian this is { operand2, operand1 } -;; For big-endian this is { operand1, operand2 } - -(define_insn "aarch64_simd_move_hi_quad_" - [(set (match_operand:VQMOV 0 "register_operand" "+w,w") - (vec_concat:VQMOV - (vec_select: - (match_dup 0) - (match_operand:VQMOV 2 "vect_par_cnst_lo_half" "")) - (match_operand: 1 "register_operand" "w,r")))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "@ - ins\\t%0.d[1], %1.d[0] - ins\\t%0.d[1], %1" - [(set_attr "type" "neon_ins")] -) - -(define_insn "aarch64_simd_move_hi_quad_be_" - [(set (match_operand:VQMOV 0 "register_operand" "+w,w") - (vec_concat:VQMOV - (match_operand: 1 "register_operand" "w,r") - (vec_select: - (match_dup 0) - (match_operand:VQMOV 2 "vect_par_cnst_lo_half" ""))))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" - "@ - ins\\t%0.d[1], %1.d[0] - ins\\t%0.d[1], %1" - [(set_attr "type" "neon_ins")] -) - -(define_expand "move_hi_quad_" - [(match_operand:VQMOV 0 "register_operand") - (match_operand: 1 "register_operand")] - "TARGET_SIMD" -{ - rtx p = aarch64_simd_vect_par_cnst_half (mode, , false); - if (BYTES_BIG_ENDIAN) - emit_insn (gen_aarch64_simd_move_hi_quad_be_ (operands[0], - operands[1], p)); - else - emit_insn (gen_aarch64_simd_move_hi_quad_ (operands[0], - operands[1], p)); - DONE; -}) - ;; Narrowing operations. (define_insn "aarch64_xtn_insn_le" @@ -1743,16 +1679,12 @@ (define_expand "vec_pack_trunc_" [(match_operand: 0 "register_operand") - (match_operand:VDN 1 "register_operand") - (match_operand:VDN 2 "register_operand")] + (match_operand:VDN 1 "general_operand") + (match_operand:VDN 2 "general_operand")] "TARGET_SIMD" { rtx tempreg = gen_reg_rtx (mode); - int lo = BYTES_BIG_ENDIAN ? 2 : 1; - int hi = BYTES_BIG_ENDIAN ? 1 : 2; - - emit_insn (gen_move_lo_quad_ (tempreg, operands[lo])); - emit_insn (gen_move_hi_quad_ (tempreg, operands[hi])); + emit_insn (gen_aarch64_vec_concat (tempreg, operands[1], operands[2])); emit_insn (gen_trunc2 (operands[0], tempreg)); DONE; }) @@ -3402,20 +3334,13 @@ (define_expand "vec_pack_trunc_df" [(set (match_operand:V2SF 0 "register_operand") - (vec_concat:V2SF - (float_truncate:SF - (match_operand:DF 1 "register_operand")) - (float_truncate:SF - (match_operand:DF 2 "register_operand")) - ))] + (vec_concat:V2SF + (float_truncate:SF (match_operand:DF 1 "general_operand")) + (float_truncate:SF (match_operand:DF 2 "general_operand"))))] "TARGET_SIMD" { rtx tmp = gen_reg_rtx (V2SFmode); - int lo = BYTES_BIG_ENDIAN ? 2 : 1; - int hi = BYTES_BIG_ENDIAN ? 1 : 2; - - emit_insn (gen_move_lo_quad_v2df (tmp, operands[lo])); - emit_insn (gen_move_hi_quad_v2df (tmp, operands[hi])); + emit_insn (gen_aarch64_vec_concatdf (tmp, operands[1], operands[2])); emit_insn (gen_aarch64_float_truncate_lo_v2sf (operands[0], tmp)); DONE; }