From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2205) id 47620385840F; Sat, 19 Feb 2022 19:07:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 47620385840F MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Tom de Vries To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-7303] [nvptx] Use _ as destination operand of atom.exch X-Act-Checkin: gcc X-Git-Author: Tom de Vries X-Git-Refname: refs/heads/master X-Git-Oldrev: 9ed52438b8ca99a0dffe74da96c2281cbc9cbb4b X-Git-Newrev: 69cb3f2abb911acebfc7ffede2ee7151a3e14a59 Message-Id: <20220219190702.47620385840F@sourceware.org> Date: Sat, 19 Feb 2022 19:07:02 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 19 Feb 2022 19:07:02 -0000 https://gcc.gnu.org/g:69cb3f2abb911acebfc7ffede2ee7151a3e14a59 commit r12-7303-g69cb3f2abb911acebfc7ffede2ee7151a3e14a59 Author: Tom de Vries Date: Tue Feb 15 14:36:26 2022 +0100 [nvptx] Use _ as destination operand of atom.exch We currently generate this code for an atomic store: ... .reg.u32 %r21; atom.exch.b32 %r21,[%r22],%r23; ... where %r21 is set but unused. Use the ptx bit bucket operand '_' instead, such that we have: ... atom.exch.b32 _,[%r22],%r23; ... [ Note that the same problem still occurs for this code: ... void atomic_store (int *ptr, int val) { __atomic_exchange_n (ptr, val, MEMMODEL_RELAXED); } ... ] Tested on nvptx. gcc/ChangeLog: 2022-02-19 Tom de Vries * config/nvptx/nvptx.cc (nvptx_reorg_uniform_simt): Handle SET insn. * config/nvptx/nvptx.md (define_insn "nvptx_atomic_store"): Rename to ... (define_insn "nvptx_atomic_store_sm70"): This. (define_insn "nvptx_atomic_store"): New define_insn. (define_expand "atomic_store"): Handle rename. Use nvptx_atomic_store instead of atomic_exchange. gcc/testsuite/ChangeLog: 2022-02-19 Tom de Vries * gcc.target/nvptx/atomic-store-1.c: Update. Diff: --- gcc/config/nvptx/nvptx.cc | 18 ++++++++++++++---- gcc/config/nvptx/nvptx.md | 25 +++++++++++++++++++------ gcc/testsuite/gcc.target/nvptx/atomic-store-1.c | 4 ++-- 3 files changed, 35 insertions(+), 12 deletions(-) diff --git a/gcc/config/nvptx/nvptx.cc b/gcc/config/nvptx/nvptx.cc index 55fab3e84cb..ed347cab70e 100644 --- a/gcc/config/nvptx/nvptx.cc +++ b/gcc/config/nvptx/nvptx.cc @@ -3291,12 +3291,22 @@ nvptx_reorg_uniform_simt () continue; rtx pat = PATTERN (insn); - gcc_assert (GET_CODE (pat) == PARALLEL); rtx master = nvptx_get_unisimt_master (); bool shuffle_p = false; - for (int i = 0; i < XVECLEN (pat, 0); i++) - shuffle_p - |= nvptx_unisimt_handle_set (XVECEXP (pat, 0, i), insn, master); + switch (GET_CODE (pat)) + { + case PARALLEL: + for (int i = 0; i < XVECLEN (pat, 0); i++) + shuffle_p + |= nvptx_unisimt_handle_set (XVECEXP (pat, 0, i), insn, master); + break; + case SET: + shuffle_p |= nvptx_unisimt_handle_set (pat, insn, master); + break; + default: + gcc_unreachable (); + } + if (shuffle_p && TARGET_PTX_6_0) { /* The shuffle is a sync, so uniformity is guaranteed. */ diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index 132ef2f1d34..f6dc817632c 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -2069,8 +2069,8 @@ if (TARGET_SM70) { - emit_insn (gen_nvptx_atomic_store (operands[0], operands[1], - operands[2])); + emit_insn (gen_nvptx_atomic_store_sm70 (operands[0], operands[1], + operands[2])); DONE; } @@ -2079,13 +2079,12 @@ /* Fall back to expand_atomic_store. */ FAIL; - rtx tmpreg = gen_reg_rtx (mode); - emit_insn (gen_atomic_exchange (tmpreg, operands[0], operands[1], - operands[2])); + emit_insn (gen_nvptx_atomic_store (operands[0], operands[1], + operands[2])); DONE; }) -(define_insn "nvptx_atomic_store" +(define_insn "nvptx_atomic_store_sm70" [(set (match_operand:SDIM 0 "memory_operand" "+m") ;; memory (unspec_volatile:SDIM [(match_operand:SDIM 1 "nvptx_nonmemory_operand" "Ri") ;; input @@ -2099,6 +2098,20 @@ } [(set_attr "atomic" "false")]) ;; Note: st is not an atomic insn. +(define_insn "nvptx_atomic_store" + [(set (match_operand:SDIM 0 "memory_operand" "+m") ;; memory + (unspec_volatile:SDIM + [(match_operand:SDIM 1 "nvptx_nonmemory_operand" "Ri") ;; input + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_ST))] + "!TARGET_SM70" + { + const char *t + = "%.\tatom%A0.exch.b%T0\t_, %0, %1;"; + return nvptx_output_atomic_insn (t, operands, 0, 2); + } + [(set_attr "atomic" "true")]) + (define_insn "atomic_fetch_add" [(set (match_operand:SDIM 1 "memory_operand" "+m") (unspec_volatile:SDIM diff --git a/gcc/testsuite/gcc.target/nvptx/atomic-store-1.c b/gcc/testsuite/gcc.target/nvptx/atomic-store-1.c index cee3815eda5..d611f2d410f 100644 --- a/gcc/testsuite/gcc.target/nvptx/atomic-store-1.c +++ b/gcc/testsuite/gcc.target/nvptx/atomic-store-1.c @@ -21,6 +21,6 @@ main() return 0; } -/* { dg-final { scan-assembler-times "atom.shared.exch.b32" 1 } } */ -/* { dg-final { scan-assembler-times "atom.shared.exch.b64" 1 } } */ +/* { dg-final { scan-assembler-times "atom.shared.exch.b32\[\t \]+_," 1 } } */ +/* { dg-final { scan-assembler-times "atom.shared.exch.b64\[\t \]+_," 1 } } */ /* { dg-final { scan-assembler-times "membar.cta" 4 } } */