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From: Matthew Malcomson <matmal01@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/morello)] morello: Implement new eh_frame landing pad layout Date: Mon, 28 Feb 2022 12:08:20 +0000 (GMT) [thread overview] Message-ID: <20220228120820.12E2D385843E@sourceware.org> (raw) https://gcc.gnu.org/g:ae2a11a94d7816ac883f96c9d9fe47c9542a7f39 commit ae2a11a94d7816ac883f96c9d9fe47c9542a7f39 Author: Stam Markianos-Wright <stam.markianos-wright@arm.com> Date: Tue Jan 18 10:47:36 2022 +0000 morello: Implement new eh_frame landing pad layout Morello uses a new layout for the call site information in the gcc_exception_table that uses a "capability marker" value and either a capability or an offset to a capability (details in the ABI DWARF extension are TBD). This patch implements only the second "indirect" schema that uses an offset to a capability, as that is the one that is intended to be stabilised and used going forwards. Section switching to output the capability in .data.rel.ro is handled in-line, rather than being queued for the end of the file (which is unfortunate, but changing it would require a much more significant overhaul of the debug output) The table now gets output like this: .section .gcc_except_table,"a",@progbits .LLSDA3: .byte 0xff .byte 0xff .byte 0x1 .uleb128 .LLSDACSE3-.LLSDACSB3 .LLSDACSB3: .uleb128 .LEHB0-.LFB3 .uleb128 .LEHE0-.LEHB0 .uleb128 0xd .Llpoff0: .section .data.rel.ro,"aw" .Llpcap0: .capinit doit+(.L10-(.LFB3)) .xword 0 .xword 0 .section .gcc_except_table .8byte .Llpcap0-.Llpoff0 .uleb128 0 .uleb128 .LEHB1-.LFB3 .uleb128 .LEHE1-.LEHB1 .uleb128 0 .uleb128 0 (the first entry has a landing pad, the second doesn't have a landing pad) Diff: --- gcc/except.c | 53 +++++++++++++++++++++- gcc/final.c | 10 +++- .../gcc.target/aarch64/c-output-template-3.c | 2 +- .../gcc.target/aarch64/c-output-template-4.c | 2 +- .../morello/label-addressing-includes-lsb.c | 4 +- 5 files changed, 64 insertions(+), 7 deletions(-) diff --git a/gcc/except.c b/gcc/except.c index 20ef7a6c178..d1b99c14570 100644 --- a/gcc/except.c +++ b/gcc/except.c @@ -222,6 +222,7 @@ static int dw2_size_of_call_site_table (int); static int sjlj_size_of_call_site_table (void); static void dw2_output_call_site_table (int, int); static void sjlj_output_call_site_table (void); +static void switch_to_exception_section (const char * ); \f void @@ -2896,7 +2897,57 @@ dw2_output_call_site_table (int cs_format, int section) "region %d start", i); dw2_asm_output_delta_uleb128 (reg_end_lab, reg_start_lab, "length"); - if (cs->landing_pad) + /* For capability targets we use an alternate schema for the call + site table. */ + if (targetm.capability_mode().exists() + && targetm.capability_mode().require() == Pmode + && cs->landing_pad) + { + char reg_cap_offs_lab[32]; + + /* First create SYMBOL_REFs to the function name, the label at + the start of the function, and the landing pad label. */ + const char * name = ggc_strdup (current_function_name()); + rtx named_function_symbol = gen_rtx_SYMBOL_REF (Pmode, name); + SYMBOL_REF_FLAGS (named_function_symbol) = SYMBOL_FLAG_LOCAL; + + rtx function_start_symbol = gen_rtx_SYMBOL_REF (Pmode, begin); + SYMBOL_REF_FLAGS (function_start_symbol) = SYMBOL_FLAG_LOCAL; + rtx landing_pad_symbol = gen_rtx_SYMBOL_REF (Pmode, + landing_pad_lab); + SYMBOL_REF_FLAGS (landing_pad_symbol) = SYMBOL_FLAG_LOCAL; + + /* Then output the capability marker value. */ + dw2_asm_output_data_uleb128 (0xd, "landing pad capability marker"); + /* Then generate a label at the current location in the call + site table. */ + char cap_lab[32]; + ASM_GENERATE_INTERNAL_LABEL (reg_cap_offs_lab, "Llpoff", + call_site_base + i); + ASM_OUTPUT_LABEL (asm_out_file, reg_cap_offs_lab); + /* Then switch to the relocatable RO data section, build the + capability as a POINTER_PLUS and output the capability. */ + switch_to_section (get_named_section (NULL, ".data.rel.ro", + 0)); + ASM_GENERATE_INTERNAL_LABEL (cap_lab, "Llpcap", + call_site_base + i); + ASM_OUTPUT_LABEL (asm_out_file, cap_lab); + rtx offset = gen_rtx_MINUS + (POmode, + drop_capability (landing_pad_symbol), + drop_capability (function_start_symbol)); + rtx landing_pad_capability + = gen_pointer_plus (Pmode, named_function_symbol, offset); + assemble_capability (landing_pad_capability, POINTER_SIZE_UNITS, + POINTER_SIZE, 1); + /* Finally, switch back to the call site table section and output + the offset between the current location and the location we + just placed the capability in. */ + switch_to_exception_section (name); + dw2_asm_output_delta (8, cap_lab, reg_cap_offs_lab, + "landing pad"); + } + else if (cs->landing_pad) dw2_asm_output_delta_uleb128 (landing_pad_lab, begin, "landing pad"); else diff --git a/gcc/final.c b/gcc/final.c index d23de908a2d..5b00a6e0f05 100644 --- a/gcc/final.c +++ b/gcc/final.c @@ -4171,8 +4171,14 @@ output_addr_const (FILE *file, rtx x) output_addr_const (file, XEXP (x, 0)); if (!CONST_INT_P (XEXP (x, 1)) || INTVAL (XEXP (x, 1)) >= 0) - fprintf (file, "+"); - output_addr_const (file, XEXP (x, 1)); + { + fprintf (file, "+"); + fputs (targetm.asm_out.open_paren, file); + output_addr_const (file, XEXP (x, 1)); + fputs (targetm.asm_out.close_paren, file); + } + else + output_addr_const (file, XEXP (x, 1)); } break; diff --git a/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c b/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c index 8bde4cbeb0c..9610d7db4c3 100644 --- a/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c +++ b/gcc/testsuite/gcc.target/aarch64/c-output-template-3.c @@ -7,4 +7,4 @@ test (void) __asm__ ("@ %c0" : : "S" (&test + 4)); } -/* { dg-final { scan-assembler "@ test\\+4" } } */ +/* { dg-final { scan-assembler "@ test\\+\\(4\\)" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/c-output-template-4.c b/gcc/testsuite/gcc.target/aarch64/c-output-template-4.c index c5a93915af1..9808a227b24 100644 --- a/gcc/testsuite/gcc.target/aarch64/c-output-template-4.c +++ b/gcc/testsuite/gcc.target/aarch64/c-output-template-4.c @@ -7,4 +7,4 @@ test (void) __asm__ ("@ %c0" : : "S" (&test + 4)); } -/* { dg-final { scan-assembler "@ test\\+4" } } */ +/* { dg-final { scan-assembler "@ test\\+\\(4\\)" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/morello/label-addressing-includes-lsb.c b/gcc/testsuite/gcc.target/aarch64/morello/label-addressing-includes-lsb.c index 2c4a9b27d13..bce89ae42ec 100644 --- a/gcc/testsuite/gcc.target/aarch64/morello/label-addressing-includes-lsb.c +++ b/gcc/testsuite/gcc.target/aarch64/morello/label-addressing-includes-lsb.c @@ -26,7 +26,7 @@ label2: } /* Ensure that we initialise labels in the constant pool with the correct form. */ -/* { dg-final { scan-assembler {capinit\tfun\+\(\(\.L\d\+1\)-fun\)} { target cheri_capability_pure } } } */ +/* { dg-final { scan-assembler {capinit\tfun\+\(\(\.L\d\+\(1\)\)-fun\)} { target cheri_capability_pure } } } */ /* Ensure that we load labels directly with the LSB set. */ -/* { dg-final { scan-assembler {adrp[^\n]*\.L\d\+1} { target cheri_capability_pure } } } */ +/* { dg-final { scan-assembler {adrp[^\n]*\.L\d\+\(1\)} { target cheri_capability_pure } } } */
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