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From: Roger Sayle <sayle@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-7416] PR middle-end/80270: ICE in extract_bit_field_1 Date: Mon, 28 Feb 2022 22:27:54 +0000 (GMT) [thread overview] Message-ID: <20220228222754.0F3A13858D20@sourceware.org> (raw) https://gcc.gnu.org/g:7e5c6edeb1b2339e10f10bee270e61dbad985800 commit r12-7416-g7e5c6edeb1b2339e10f10bee270e61dbad985800 Author: Roger Sayle <roger@nextmovesoftware.com> Date: Mon Feb 28 22:26:43 2022 +0000 PR middle-end/80270: ICE in extract_bit_field_1 This patch fixes PR middle-end/80270, an ICE-on-valid regression, where performing a bitfield extraction on a variable explicitly stored in a hard register by the user causes a segmentation fault during RTL expansion. Nearly identical source code without the "asm" qualifier compiles fine. The point of divergence is in simplify_gen_subreg which tries to avoid creating non-trivial SUBREGs of hard registers, to avoid problems during register allocation. This suggests the simple solution proposed here, to copy hard registers to a new pseudo in extract_integral_bit_field, just before calling simplify_gen_subreg. 2022-02-28 Roger Sayle <roger@nextmovesoftware.com> Eric Botcazou <ebotcazou@adacore.com> gcc/ChangeLog PR middle-end/80270 * expmed.cc (extract_integral_bit_field): If OP0 is a hard register, copy it to a pseudo before calling simplify_gen_subreg. gcc/testsuite/ChangeLog * gcc.target/i386/pr80270.c: New test case. Diff: --- gcc/expmed.cc | 4 ++++ gcc/testsuite/gcc.target/i386/pr80270.c | 21 +++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/gcc/expmed.cc b/gcc/expmed.cc index 80a16cedfd5..ed39c88bd04 100644 --- a/gcc/expmed.cc +++ b/gcc/expmed.cc @@ -1975,6 +1975,10 @@ extract_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode, unsignedp, reverse); return convert_extracted_bit_field (target, mode, tmode, unsignedp); } + /* If OP0 is a hard register, copy it to a pseudo before calling + simplify_gen_subreg. */ + if (REG_P (op0) && HARD_REGISTER_P (op0)) + op0 = copy_to_reg (op0); op0 = simplify_gen_subreg (word_mode, op0, op0_mode.require (), bitnum / BITS_PER_WORD * UNITS_PER_WORD); op0_mode = word_mode; diff --git a/gcc/testsuite/gcc.target/i386/pr80270.c b/gcc/testsuite/gcc.target/i386/pr80270.c new file mode 100644 index 00000000000..89e9c33d090 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr80270.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse" } */ + +typedef int v8 __attribute__((vector_size(8))); +struct S1 { + v8 s1f; +}; +struct S2 { + struct S1 s2f1; + v8 s2f2; +}; + +extern void foo(int); + +void bar() { + int tmp, i = 3; + register struct S2 b asm("xmm0"); + tmp = b.s2f1.s1f[i]; + foo(tmp); +} +
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