From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7861) id A9CF63858D20; Tue, 1 Mar 2022 01:36:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A9CF63858D20 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Hongyu Wang To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-7419] i386: Fix V8HF vector init under -mno-avx [PR 104664] X-Act-Checkin: gcc X-Git-Author: Hongyu Wang X-Git-Refname: refs/heads/master X-Git-Oldrev: a35f16971b4ba047779ec8a3723dd1bfd9ecdf3d X-Git-Newrev: e2385690a3ead66744e51115966f25f9c05bb3e2 Message-Id: <20220301013601.A9CF63858D20@sourceware.org> Date: Tue, 1 Mar 2022 01:36:01 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Mar 2022 01:36:01 -0000 https://gcc.gnu.org/g:e2385690a3ead66744e51115966f25f9c05bb3e2 commit r12-7419-ge2385690a3ead66744e51115966f25f9c05bb3e2 Author: Hongyu Wang Date: Mon Feb 28 15:09:59 2022 +0800 i386: Fix V8HF vector init under -mno-avx [PR 104664] For V8HFmode vector init with HFmode, do not directly emits V8HF move with subreg, which may cause reload to assign general register to move src. gcc/ChangeLog: PR target/104664 * config/i386/i386-expand.cc (ix86_expand_vector_init_duplicate): Use vec_setv8hf_0 for HF to V8HFmode move instead of subreg. gcc/testsuite/ChangeLog: PR target/104664 * gcc.target/i386/pr104664.c: New test. Diff: --- gcc/config/i386/i386-expand.cc | 7 ++++++- gcc/testsuite/gcc.target/i386/pr104664.c | 16 ++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index faa0191c6dd..530f83fab88 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -14899,7 +14899,12 @@ ix86_expand_vector_init_duplicate (bool mmx_ok, machine_mode mode, dperm.one_operand_p = true; if (mode == V8HFmode) - tmp1 = lowpart_subreg (V8HFmode, force_reg (HFmode, val), HFmode); + { + tmp1 = force_reg (HFmode, val); + tmp2 = gen_reg_rtx (mode); + emit_insn (gen_vec_setv8hf_0 (tmp2, CONST0_RTX (mode), tmp1)); + tmp1 = gen_lowpart (mode, tmp2); + } else { /* Extend to SImode using a paradoxical SUBREG. */ diff --git a/gcc/testsuite/gcc.target/i386/pr104664.c b/gcc/testsuite/gcc.target/i386/pr104664.c new file mode 100644 index 00000000000..8a3d6c7cc85 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr104664.c @@ -0,0 +1,16 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-march=x86-64 -mtune=generic -Og -ffinite-math-only" } */ + +typedef _Float128 __attribute__((__vector_size__ (16))) U; +typedef _Float128 __attribute__((__vector_size__ (32))) V; +typedef _Float16 __attribute__((__vector_size__ (16))) W; + +U u; +V v; +W w; + +void +foo (void) +{ + w *= (W)(u == __builtin_shufflevector (v, u, 2)); +}