From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 17F84385841D; Wed, 2 Mar 2022 18:13:08 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 17F84385841D Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work079)] Revert patches. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work079 X-Git-Oldrev: 1a10e0bc71561d4b4624b7fb9a8d59de49aa3a21 X-Git-Newrev: 8f1243ed62a38f7edd24ce2615eb5a29b9233b95 Message-Id: <20220302181308.17F84385841D@sourceware.org> Date: Wed, 2 Mar 2022 18:13:08 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Mar 2022 18:13:08 -0000 https://gcc.gnu.org/g:8f1243ed62a38f7edd24ce2615eb5a29b9233b95 commit 8f1243ed62a38f7edd24ce2615eb5a29b9233b95 Author: Michael Meissner Date: Wed Mar 2 13:07:44 2022 -0500 Revert patches. 2022-03-01 Michael Meissner gcc/ Revert patch. PR target/103109 * config/rs6000/rs6000.md (su_int32): New code attribute. (mul3): Convert into define_insn_and_split. (maddld4): Add generator function. (mulditi3_adddi3): New insn. (mulditi3_add_const): New insn. (addti3): Convert into define_insn_and_split. (subti3): Likewise. 2022-02-25 Michael Meissner gcc/ Revert patch. PR target/104698 * config/rs6000/vsx.md (mtvsrdd_diti_w1): Delete. (extendditi2): Replace with code to deal with both GPR registers and with altivec registers. Diff: --- gcc/config/rs6000/rs6000.md | 160 +++++--------------------------------------- gcc/config/rs6000/vsx.md | 73 ++++++-------------- 2 files changed, 38 insertions(+), 195 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b5fc1855c35..fdfbc6566a5 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -676,9 +676,6 @@ (float "") (unsigned_float "uns")]) -(define_code_attr su_int32 [(sign_extend "s32bit_cint_operand") - (zero_extend "c32bit_cint_operand")]) - ; Various instructions that come in SI and DI forms. ; A generic w/d attribute, for things like cmpw/cmpd. (define_mode_attr wd [(QI "b") @@ -3202,16 +3199,13 @@ "mulhw %0,%1,%2" [(set_attr "type" "mul")]) -(define_insn_and_split "mul3" - [(set (match_operand: 0 "gpc_reg_operand" "=&r") +(define_expand "mul3" + [(set (match_operand: 0 "gpc_reg_operand") (mult: (any_extend: - (match_operand:GPR 1 "gpc_reg_operand" "r")) + (match_operand:GPR 1 "gpc_reg_operand")) (any_extend: - (match_operand:GPR 2 "gpc_reg_operand" "r"))))] + (match_operand:GPR 2 "gpc_reg_operand"))))] "!(mode == SImode && TARGET_POWERPC64)" - "#" - "&& 1" - [(pc)] { rtx l = gen_reg_rtx (mode); rtx h = gen_reg_rtx (mode); @@ -3220,10 +3214,9 @@ emit_move_insn (gen_lowpart (mode, operands[0]), l); emit_move_insn (gen_highpart (mode, operands[0]), h); DONE; -} - [(set_attr "length" "8")]) +}) -(define_insn "maddld4" +(define_insn "*maddld4" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (plus:GPR (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") (match_operand:GPR 2 "gpc_reg_operand" "r")) @@ -3232,113 +3225,6 @@ "maddld %0,%1,%2,%3" [(set_attr "type" "mul")]) -(define_insn_and_split "*mulditi3_adddi3" - [(set (match_operand:TI 0 "gpc_reg_operand" "=&r") - (plus:TI - (mult:TI - (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r")) - (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r"))) - (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r"))))] - "TARGET_MADDLD && TARGET_POWERPC64" - "#" - "&& 1" - [(pc)] -{ - rtx dest = operands[0]; - rtx dest_hi = gen_highpart (DImode, dest); - rtx dest_lo = gen_lowpart (DImode, dest); - rtx op1 = operands[1]; - rtx op2 = operands[2]; - rtx op3 = operands[3]; - rtx tmp_hi, tmp_lo; - - if (can_create_pseudo_p ()) - { - tmp_hi = gen_reg_rtx (DImode); - tmp_lo = gen_reg_rtx (DImode); - } - else - { - tmp_hi = dest_hi; - tmp_lo = dest_lo; - } - - emit_insn (gen_mulditi3_adddi3_upper (tmp_hi, op1, op2, op3)); - emit_insn (gen_maddlddi4 (tmp_lo, op1, op2, op3)); - - if (can_create_pseudo_p ()) - { - emit_move_insn (dest_hi, tmp_hi); - emit_move_insn (dest_lo, tmp_lo); - } - DONE; -} - [(set_attr "length" "8")]) - -;; Optimize 128-bit multiply with zero/sign extend and adding a constant. We -;; force the constant into a register to generate li, maddhd, and maddld, -;; instead of mulld, mulhd, addic, and addze. We can't combine this pattern -;; with the pattern that handles registers, since constants don't have a sign -;; or zero extend around them. -(define_insn_and_split "*mulditi3_add_const" - [(set (match_operand:TI 0 "gpc_reg_operand" "=&r") - (plus:TI - (mult:TI - (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r")) - (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r"))) - (match_operand 3 "" "r")))] - "TARGET_MADDLD && TARGET_POWERPC64 -" - "#" - "&& 1" - [(pc)] -{ - rtx dest = operands[0]; - rtx dest_hi = gen_highpart (DImode, dest); - rtx dest_lo = gen_lowpart (DImode, dest); - rtx op1 = operands[1]; - rtx op2 = operands[2]; - rtx op3 = force_reg (DImode, operands[3]); - rtx tmp_hi, tmp_lo; - - if (can_create_pseudo_p ()) - { - tmp_hi = gen_reg_rtx (DImode); - tmp_lo = gen_reg_rtx (DImode); - } - else - { - tmp_hi = dest_hi; - tmp_lo = dest_lo; - } - - emit_insn (gen_mulditi3_adddi3_upper (tmp_hi, op1, op2, op3)); - emit_insn (gen_maddlddi4 (tmp_lo, op1, op2, op3)); - - if (can_create_pseudo_p ()) - { - emit_move_insn (dest_hi, tmp_hi); - emit_move_insn (dest_lo, tmp_lo); - } - DONE; -} - [(set_attr "length" "8")]) - -(define_insn "mulditi3_adddi3_upper" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (truncate:DI - (lshiftrt:TI - (plus:TI - (mult:TI - (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r")) - (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r"))) - (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r"))) - (const_int 64))))] - "TARGET_MADDLD && TARGET_POWERPC64" - "maddhd %0,%1,%2,%3" - [(set_attr "type" "mul") - (set_attr "size" "64")]) - (define_insn "udiv3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") @@ -7143,19 +7029,12 @@ ;; allocator from allocating registers that overlap with the inputs ;; (for example, having an input in 7,8 and an output in 6,7). We ;; also allow for the output being the same as one of the inputs. -;; -;; Addti3/subti3 are define_insn_and_splits instead of define_expand, to allow -;; for combine to make things like multiply and add with extend operations. - -(define_insn_and_split "addti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r") - (plus:TI (match_operand:TI 1 "gpc_reg_operand" "r,0,r") - (match_operand:TI 2 "reg_or_short_operand" "rn,r,0"))) - (clobber (reg:DI CA_REGNO))] + +(define_expand "addti3" + [(set (match_operand:TI 0 "gpc_reg_operand") + (plus:TI (match_operand:TI 1 "gpc_reg_operand") + (match_operand:TI 2 "reg_or_short_operand")))] "TARGET_64BIT" - "#" - "&& 1" - [(pc)] { rtx lo0 = gen_lowpart (DImode, operands[0]); rtx lo1 = gen_lowpart (DImode, operands[1]); @@ -7172,17 +7051,13 @@ emit_insn (gen_adddi3_carry (lo0, lo1, lo2)); emit_insn (gen_adddi3_carry_in (hi0, hi1, hi2)); DONE; -} - [(set_attr "length" "8")]) +}) -(define_insn_and_split "subti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r") - (minus:TI (match_operand:TI 1 "reg_or_short_operand" "rn,0,r") - (match_operand:TI 2 "gpc_reg_operand" "r,r,0")))] +(define_expand "subti3" + [(set (match_operand:TI 0 "gpc_reg_operand") + (minus:TI (match_operand:TI 1 "reg_or_short_operand") + (match_operand:TI 2 "gpc_reg_operand")))] "TARGET_64BIT" - "#" - "&& 1" - [(pc)] { rtx lo0 = gen_lowpart (DImode, operands[0]); rtx lo1 = gen_lowpart (DImode, operands[1]); @@ -7199,8 +7074,7 @@ emit_insn (gen_subfdi3_carry (lo0, lo2, lo1)); emit_insn (gen_subfdi3_carry_in (hi0, hi2, hi1)); DONE; -} - [(set_attr "length" "8")]) +}) ;; 128-bit logical operations expanders diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 62464f67f4d..b53de103872 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5023,58 +5023,15 @@ DONE; }) -;; Sign extend DI to TI. We provide both GPR targets and Altivec targets. If -;; the register allocator prefers the GPRs, we won't have to move the value to -;; the altivec registers, do the vextsd2q instruction and move it back. If we -;; aren't compiling for 64-bit power10, don't provide the service and let the -;; machine independent code handle the extension. -(define_insn_and_split "extendditi2" - [(set (match_operand:TI 0 "register_operand" "=r,r,v,v,v") - (sign_extend:TI (match_operand:DI 1 "input_operand" "r,m,r,wa,Z"))) - (clobber (reg:DI CA_REGNO))] - "TARGET_POWERPC64 && TARGET_POWER10" - "#" - "&& reload_completed" - [(pc)] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - int dest_regno = reg_or_subregno (dest); - - /* Handle conversion to GPR registers. Load up the low part and then do - a sign extension to the upper part. */ - if (INT_REGNO_P (dest_regno)) - { - rtx dest_hi = gen_highpart (DImode, dest); - rtx dest_lo = gen_lowpart (DImode, dest); - - emit_move_insn (dest_lo, src); - emit_insn (gen_ashrdi3 (dest_hi, dest_lo, GEN_INT (63))); - DONE; - } - - /* For conversion to Altivec register, generate either a splat operation or - a load rightmost double word instruction. Both instructions gets the - DImode value into the lower 64 bits, and then do the vextsd2q - instruction. */ - else if (ALTIVEC_REGNO_P (dest_regno)) - { - if (MEM_P (src)) - emit_insn (gen_vsx_lxvrdx (dest, src)); - else - { - rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno); - emit_insn (gen_vsx_splat_v2di (dest_v2di, src)); - } - - emit_insn (gen_extendditi2_vector (dest, dest)); - DONE; - } - - else - gcc_unreachable (); -} - [(set_attr "length" "8")]) +;; ISA 3.1 vector sign extend +;; Move DI value from GPR to TI mode in VSX register, word 1. +(define_insn "mtvsrdd_diti_w1" + [(set (match_operand:TI 0 "register_operand" "=wa") + (unspec:TI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_MTVSRD_DITI_W1))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "mtvsrdd %x0,0,%1" + [(set_attr "type" "vecmove")]) ;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg (define_insn "extendditi2_vector" @@ -5085,6 +5042,18 @@ "vextsd2q %0,%1" [(set_attr "type" "vecexts")]) +(define_expand "extendditi2" + [(set (match_operand:TI 0 "gpc_reg_operand") + (sign_extend:DI (match_operand:DI 1 "gpc_reg_operand")))] + "TARGET_POWER10" + { + /* Move 64-bit src from GPR to vector reg and sign extend to 128-bits. */ + rtx temp = gen_reg_rtx (TImode); + emit_insn (gen_mtvsrdd_diti_w1 (temp, operands[1])); + emit_insn (gen_extendditi2_vector (operands[0], temp)); + DONE; + }) + ;; ISA 3.0 Binary Floating-Point Support