From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2153) id 3D90B3858C74; Mon, 7 Mar 2022 08:41:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3D90B3858C74 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Jakub Jelinek To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-7509] i386: Fix up cond_{and,ior,xor,mul}* [PR104779] X-Act-Checkin: gcc X-Git-Author: Jakub Jelinek X-Git-Refname: refs/heads/master X-Git-Oldrev: 0f0b42896196315acfc636b1e535cda4ee283646 X-Git-Newrev: 3bd11f791e08a5676f176d632c729d147f12dcaa Message-Id: <20220307084137.3D90B3858C74@sourceware.org> Date: Mon, 7 Mar 2022 08:41:37 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Mar 2022 08:41:37 -0000 https://gcc.gnu.org/g:3bd11f791e08a5676f176d632c729d147f12dcaa commit r12-7509-g3bd11f791e08a5676f176d632c729d147f12dcaa Author: Jakub Jelinek Date: Mon Mar 7 09:40:51 2022 +0100 i386: Fix up cond_{and,ior,xor,mul}* [PR104779] The following testcase ICEs, because the cond_andv* expander has vector_operand predicates in both of the commutative inputs and calls gen_andv*_mask which calls ix86_binary_operator_ok in its condition, but nothing calls ix86_fixup_binary_operands_no_copy during the expansion, which means cond_* accepts even operands like 2 MEMs which then can't be matched. The following patch handles it like most other insns that the other cond_* patterns use - by having a separate define_expand that calls ix86_fixup_binary_operands_no_copy and define_ins with ix86_binary_operator_ok. 2022-03-07 Jakub Jelinek PR target/104779 * config/i386/sse.md (avx512dq_mul3): New define_expand pattern. Rename define_insn to ... (*avx512dq_mul3): ... this. (3_mask): New any_logic define_expand pattern. (3): Rename to ... (*3): ... this. * gcc.target/i386/pr104779.c: New test. Diff: --- gcc/config/i386/sse.md | 23 +++++++++++++++++++++-- gcc/testsuite/gcc.target/i386/pr104779.c | 27 +++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 3066ea3734a..0076475d7ba 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15210,7 +15210,15 @@ DONE; }) -(define_insn "avx512dq_mul3" +(define_expand "avx512dq_mul3" + [(set (match_operand:VI8_AVX512VL 0 "register_operand") + (mult:VI8_AVX512VL + (match_operand:VI8_AVX512VL 1 "bcst_vector_operand") + (match_operand:VI8_AVX512VL 2 "bcst_vector_operand")))] + "TARGET_AVX512DQ && " + "ix86_fixup_binary_operands_no_copy (MULT, mode, operands);") + +(define_insn "*avx512dq_mul3" [(set (match_operand:VI8_AVX512VL 0 "register_operand" "=v") (mult:VI8_AVX512VL (match_operand:VI8_AVX512VL 1 "bcst_vector_operand" "%v") @@ -16824,7 +16832,18 @@ DONE; }) -(define_insn "3" +(define_expand "3_mask" + [(set (match_operand:VI48_AVX512VL 0 "register_operand") + (vec_merge:VI48_AVX512VL + (any_logic:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "bcst_vector_operand") + (match_operand:VI48_AVX512VL 2 "bcst_vector_operand")) + (match_operand:VI48_AVX512VL 3 "nonimm_or_0_operand") + (match_operand: 4 "register_operand")))] + "TARGET_AVX512F" + "ix86_fixup_binary_operands_no_copy (, mode, operands);") + +(define_insn "*3" [(set (match_operand:VI48_AVX_AVX512F 0 "register_operand" "=x,x,v") (any_logic:VI48_AVX_AVX512F (match_operand:VI48_AVX_AVX512F 1 "bcst_vector_operand" "%0,x,v") diff --git a/gcc/testsuite/gcc.target/i386/pr104779.c b/gcc/testsuite/gcc.target/i386/pr104779.c new file mode 100644 index 00000000000..2dd8ec6a183 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr104779.c @@ -0,0 +1,27 @@ +/* PR target/104779 */ +/* { dg-do compile } */ +/* { dg-options "-O1 --param sccvn-max-alias-queries-per-access=0" } */ + +__attribute__ ((simd)) int +foo (int x, int y, int z) +{ + return (x & y) * !!z; +} + +__attribute__ ((simd)) int +bar (int x, int y, int z) +{ + return (x | y) * !!z; +} + +__attribute__ ((simd)) int +baz (int x, int y, int z) +{ + return (x ^ y) * !!z; +} + +__attribute__ ((simd, target ("avx512dq"))) long +qux (long x, long y, long z) +{ + return (x * y) * !!z; +}