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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work080)] Generate vadduqm and vsubuqm. Date: Mon, 7 Mar 2022 23:44:42 +0000 (GMT) [thread overview] Message-ID: <20220307234442.2B1043857C69@sourceware.org> (raw) https://gcc.gnu.org/g:6f89fc2fd78421b286eeb18dc40c9b63a0849480 commit 6f89fc2fd78421b286eeb18dc40c9b63a0849480 Author: Michael Meissner <meissner@linux.ibm.com> Date: Mon Mar 7 18:44:25 2022 -0500 Generate vadduqm and vsubuqm. This patch generates the vadduqm and vsubuqm instructions if the result of the 128-bit add and subtract is in an altivec register instead of a GPR register. 2022-03-07 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/rs6000.md (addti3): Generate vadduqm on power8. (subti3): Generate vsubuqm on power8. Diff: --- gcc/config/rs6000/rs6000.md | 51 +++++++++++++++++++++++++++++++-------------- 1 file changed, 35 insertions(+), 16 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index da7367ee642..6eee8d4e393 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7149,14 +7149,27 @@ ;; Addti3/subti3 are define_insn_and_splits instead of define_expand, to allow ;; for combine to make things like multiply and add with extend operations. +;; Define the TImode operations that can be done in a small number +;; of instructions. The & constraints are to prevent the register +;; allocator from allocating registers that overlap with the inputs +;; (for example, having an input in 7,8 and an output in 6,7). We +;; also allow for the output being the same as one of the inputs. +;; +;; Addti3/subti3 are define_insn_and_splits instead of define_expand, to allow +;; for combine to make things like multiply and add with extend operations. + (define_insn_and_split "addti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r") - (plus:TI (match_operand:TI 1 "gpc_reg_operand" "r,0,r") - (match_operand:TI 2 "reg_or_short_operand" "rn,r,0"))) + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r,v") + (plus:TI (match_operand:TI 1 "gpc_reg_operand" "r,0,r,v") + (match_operand:TI 2 "reg_or_short_operand" "rn,r,0,v"))) (clobber (reg:DI CA_REGNO))] "TARGET_64BIT" - "#" - "&& 1" + "@ + # + # + # + vadduqm %0,%1,%2" + "&& reload_completed && !altivec_register_operand (operands[0], TImode)" [(pc)] { rtx lo0 = gen_lowpart (DImode, operands[0]); @@ -7175,17 +7188,22 @@ emit_insn (gen_adddi3_carry_in (hi0, hi1, hi2)); DONE; } - [(set_attr "length" "8") - (set_attr "type" "add") - (set_attr "size" "128")]) + [(set_attr "length" "8,8,8,*") + (set_attr "type" "add,add,add,veccmpsimple") + (set_attr "size" "128") + (set_attr "isa" "*,*,*,p8v")]) (define_insn_and_split "subti3" - [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r") - (minus:TI (match_operand:TI 1 "reg_or_short_operand" "rn,0,r") - (match_operand:TI 2 "gpc_reg_operand" "r,r,0")))] + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r,v") + (minus:TI (match_operand:TI 1 "reg_or_short_operand" "rn,0,r,v") + (match_operand:TI 2 "gpc_reg_operand" "r,r,0,v")))] "TARGET_64BIT" - "#" - "&& 1" + "@ + # + # + # + vsubuqm %0,%1,%2" + "&& reload_completed && !altivec_register_operand (operands[0], TImode)" [(pc)] { rtx lo0 = gen_lowpart (DImode, operands[0]); @@ -7204,9 +7222,10 @@ emit_insn (gen_subfdi3_carry_in (hi0, hi2, hi1)); DONE; } - [(set_attr "length" "8") - (set_attr "type" "add") - (set_attr "size" "128")]) + [(set_attr "length" "8,8,8,*") + (set_attr "type" "add,add,add,veccmpsimple") + (set_attr "size" "128") + (set_attr "isa" "*,*,*,p8v")]) \f ;; 128-bit logical operations expanders
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