[gcc(refs/users/meissner/heads/work081)] Revert patch.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:dc6d9598456fbb08438d6fdc953ecf1fbbadf899

commit dc6d9598456fbb08438d6fdc953ecf1fbbadf899
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Mar 9 12:14:16 2022 -0500

    Revert patch.
    
    2022-03-09   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            Revert patch.
            PR target/102059
            * config/rs6000/rs6000-cpus.def (OTHER_FUSION_MASKS): Delete.
            (ISA_3_0_MASKS_SERVER): Don't clear the fusion masks.
            (POWERPC_MASKS): Remove OPTION_MASK_P8_FUSION.
            * config/rs6000/rs6000.cc (rs6000_option_override_internal):
            Change how power8 fusion options are set from being an option mask
            to being separate variables.
            (rs6000_opt_masks): Remove -mpower8-fusion and
            -mpower8-fusion-sign.
            * config/rs6000/rs6000.h (MASK_P8_FUSION): Delete.
            * config/rs6000/rs6000.opt (-mpower8-fusion): Change from being an
            option mask to being a separate variable.
            (-mpower8-fusion-sign): Likewise.
    
    gcc/testsuite/
            Revert patch.
            PR target/102059
            * gcc.target/powerpc/pr102059-4.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def             | 22 ++++++++++------
 gcc/config/rs6000/rs6000.cc                   | 36 +++++++++++++++++++++------
 gcc/config/rs6000/rs6000.h                    |  1 +
 gcc/config/rs6000/rs6000.opt                  |  4 +--
 gcc/testsuite/gcc.target/powerpc/pr102059-4.c | 23 -----------------
 5 files changed, 47 insertions(+), 39 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index ea15b8f812c..963947f6939 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -43,7 +43,9 @@
 				 | OPTION_MASK_ALTIVEC			\
 				 | OPTION_MASK_VSX)
 
-/* For now, don't provide an embedded version of ISA 2.07.  */
+/* For now, don't provide an embedded version of ISA 2.07.  Do not set power8
+   fusion here, instead set it in rs6000.cc if we are tuning for a power8
+   system.  */
 #define ISA_2_7_MASKS_SERVER	(ISA_2_6_MASKS_SERVER			\
 				 | OPTION_MASK_P8_VECTOR		\
 				 | OPTION_MASK_CRYPTO			\
@@ -52,14 +54,19 @@
 				 | OPTION_MASK_QUAD_MEMORY		\
 				 | OPTION_MASK_QUAD_MEMORY_ATOMIC)
 
+/* ISA masks setting fusion options.  */
+#define OTHER_FUSION_MASKS	(OPTION_MASK_P8_FUSION			\
+				 | OPTION_MASK_P8_FUSION_SIGN)
+
 /* Add ISEL back into ISA 3.0, since it is supposed to be a win.  Do not add
    FLOAT128_HW here until we are ready to make -mfloat128 on by default.  */
-#define ISA_3_0_MASKS_SERVER	(ISA_2_7_MASKS_SERVER			\
-				 | OPTION_MASK_ISEL			\
-				 | OPTION_MASK_MODULO			\
-				 | OPTION_MASK_P9_MINMAX		\
-				 | OPTION_MASK_P9_MISC			\
-				 | OPTION_MASK_P9_VECTOR)		\
+#define ISA_3_0_MASKS_SERVER	((ISA_2_7_MASKS_SERVER			\
+				  | OPTION_MASK_ISEL			\
+				  | OPTION_MASK_MODULO			\
+				  | OPTION_MASK_P9_MINMAX		\
+				  | OPTION_MASK_P9_MISC			\
+				  | OPTION_MASK_P9_VECTOR)		\
+				 & ~OTHER_FUSION_MASKS)
 
 /* Support for the IEEE 128-bit floating point hardware requires a lot of the
    VSX instructions that are part of ISA 3.0.  */
@@ -133,6 +140,7 @@
 				 | OPTION_MASK_MODULO			\
 				 | OPTION_MASK_MULHW			\
 				 | OPTION_MASK_NO_UPDATE		\
+				 | OPTION_MASK_P8_FUSION		\
 				 | OPTION_MASK_P8_VECTOR		\
 				 | OPTION_MASK_P9_MINMAX		\
 				 | OPTION_MASK_P9_MISC			\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index cb27b1bee05..3afe78f5d04 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4043,17 +4043,37 @@ rs6000_option_override_internal (bool global_init_p)
   /* Enable power8 fusion if we are tuning for power8, even if we aren't
      generating power8 instructions.  Power9 does not optimize power8 fusion
      cases.  */
-  if (!OPTION_SET_P (TARGET_P8_FUSION))
-    TARGET_P8_FUSION = (processor_target_table[tune_index].processor
-			== PROCESSOR_POWER8);
+  if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
+    {
+      if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
+	rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
+      else
+	rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
+    }
+
+  /* Setting additional fusion flags turns on base fusion.  */
+  if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
+    {
+      if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
+	{
+	  if (TARGET_P8_FUSION_SIGN)
+	    error ("%qs requires %qs", "-mpower8-fusion-sign",
+		   "-mpower8-fusion");
+
+	  rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
+	}
+      else
+	rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
+    }
 
   /* Power8 does not fuse sign extended loads with the addis.  If we are
      optimizing at high levels for speed, convert a sign extended load into a
      zero extending load, and an explicit sign extension.  */
-  if (!OPTION_SET_P (TARGET_P8_FUSION_SIGN))
-    TARGET_P8_FUSION_SIGN = (TARGET_P8_FUSION
-			     && optimize_function_for_speed_p (cfun)
-			     && optimize >= 3);
+  if (TARGET_P8_FUSION
+      && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
+      && optimize_function_for_speed_p (cfun)
+      && optimize >= 3)
+    rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
 
   /* ISA 3.0 vector instructions include ISA 2.07.  */
   if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
@@ -23963,6 +23983,8 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "pcrel-opt",		OPTION_MASK_PCREL_OPT,		false, true  },
   { "popcntb",			OPTION_MASK_POPCNTB,		false, true  },
   { "popcntd",			OPTION_MASK_POPCNTD,		false, true  },
+  { "power8-fusion",		OPTION_MASK_P8_FUSION,		false, true  },
+  { "power8-fusion-sign",	OPTION_MASK_P8_FUSION_SIGN,	false, true  },
   { "power8-vector",		OPTION_MASK_P8_VECTOR,		false, true  },
   { "power9-minmax",		OPTION_MASK_P9_MINMAX,		false, true  },
   { "power9-misc",		OPTION_MASK_P9_MISC,		false, true  },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 686d7a473e0..17af314416c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -517,6 +517,7 @@ extern int rs6000_vector_align[];
 #define MASK_FLOAT128_KEYWORD		OPTION_MASK_FLOAT128_KEYWORD
 #define MASK_FLOAT128_HW		OPTION_MASK_FLOAT128_HW
 #define MASK_FPRND			OPTION_MASK_FPRND
+#define MASK_P8_FUSION			OPTION_MASK_P8_FUSION
 #define MASK_HARD_FLOAT			OPTION_MASK_HARD_FLOAT
 #define MASK_HTM			OPTION_MASK_HTM
 #define MASK_ISEL			OPTION_MASK_ISEL
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 3327bbb2194..4931d781c4e 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -475,11 +475,11 @@ mvsx-timode
 Target RejectNegative Undocumented Ignore
 
 mpower8-fusion
-Target Var(TARGET_P8_FUSION)
+Target Mask(P8_FUSION) Var(rs6000_isa_flags)
 Fuse certain integer operations together for better performance on power8.
 
 mpower8-fusion-sign
-Target Undocumented Var(TARGET_P8_FUSION_SIGN)
+Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
 Allow sign extension in fusion operations.
 
 mpower8-vector
diff --git a/gcc/testsuite/gcc.target/powerpc/pr102059-4.c b/gcc/testsuite/gcc.target/powerpc/pr102059-4.c
deleted file mode 100644
index 5fe66f8af4b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr102059-4.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
-/* { dg-require-effective-target power10_ok } */
-
-/* Verify that power10 can explicity include functions compiled for power8.
-   The issue was -mcpu=power8 enables -mpower8-fusion, but -mcpu=power9 or
-   -mcpu=power10 do not set power8-fusion by default.  Thus when doing this
-   compilation, they would get an error that the inline function failed in its
-   inlining due to having incompatible options.  */
-
-static inline int __attribute__ ((always_inline,target("cpu=power8")))
-foo (int *b)
-{
-  *b += 10;
-  return *b;
-}
-
-int
-bar (int *a)
-{
-  *a = foo (a);
-  return 0;
-}