From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id D90413858C74; Wed, 9 Mar 2022 21:37:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D90413858C74 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work081)] Revert patch. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work081 X-Git-Oldrev: 6f88c98724d88a323489eeb1b25777f41f0b949b X-Git-Newrev: 7f3bdc191435ee53cfaaa1f88c3a8cb9ed69e91a Message-Id: <20220309213745.D90413858C74@sourceware.org> Date: Wed, 9 Mar 2022 21:37:45 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 09 Mar 2022 21:37:46 -0000 https://gcc.gnu.org/g:7f3bdc191435ee53cfaaa1f88c3a8cb9ed69e91a commit 7f3bdc191435ee53cfaaa1f88c3a8cb9ed69e91a Author: Michael Meissner Date: Wed Mar 9 16:36:58 2022 -0500 Revert patch. 2022-03-09 Michael Meissner gcc/ Revert patch. PR target/102059 * config/rs6000/rs6000-cpus.def (OTHER_FUSION_MASKS): Delete. (ISA_3_0_MASKS_SERVER): Don't clear the fusion masks. (POWERPC_MASKS): Remove OPTION_MASK_P8_FUSION. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Delete code that set the power8 fusion options automatically. (rs6000_opt_masks): Allow #pragma target and attribute target to set power8-fusion and power8-fusion-sign, but these no longer represent options that the user can set. * config/rs6000/rs6000.h (TARGET_P8_FUSION): New macro. (TARGET_P8_FUSION_SIGN): Likewise. (MASK_P8_FUSION): Delete. * config/rs6000/rs6000.opt (-mpower8-fusion): Recognize the option but ignore the no form and warn that the option was removed for the regular form. (-mpower8-fusion-sign): Likewise. * doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mpower8-fusion and -mpower8-fusion-sign. gcc/testsuite/ Revert patch. PR target/102059 * gcc.target/powerpc/pr102059-4.c: New test. Diff: --- gcc/config/rs6000/rs6000-cpus.def | 22 ++++++++----- gcc/config/rs6000/rs6000.cc | 45 ++++++++++++++++++++++----- gcc/config/rs6000/rs6000.h | 14 +-------- gcc/config/rs6000/rs6000.opt | 14 +++------ gcc/doc/invoke.texi | 13 ++++++-- gcc/testsuite/gcc.target/powerpc/pr102059-4.c | 23 -------------- 6 files changed, 68 insertions(+), 63 deletions(-) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index a05b2d8c41a..963947f6939 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -43,7 +43,9 @@ | OPTION_MASK_ALTIVEC \ | OPTION_MASK_VSX) -/* For now, don't provide an embedded version of ISA 2.07. */ +/* For now, don't provide an embedded version of ISA 2.07. Do not set power8 + fusion here, instead set it in rs6000.cc if we are tuning for a power8 + system. */ #define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_CRYPTO \ @@ -52,14 +54,19 @@ | OPTION_MASK_QUAD_MEMORY \ | OPTION_MASK_QUAD_MEMORY_ATOMIC) +/* ISA masks setting fusion options. */ +#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \ + | OPTION_MASK_P8_FUSION_SIGN) + /* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add FLOAT128_HW here until we are ready to make -mfloat128 on by default. */ -#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \ - | OPTION_MASK_ISEL \ - | OPTION_MASK_MODULO \ - | OPTION_MASK_P9_MINMAX \ - | OPTION_MASK_P9_MISC \ - | OPTION_MASK_P9_VECTOR) +#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \ + | OPTION_MASK_ISEL \ + | OPTION_MASK_MODULO \ + | OPTION_MASK_P9_MINMAX \ + | OPTION_MASK_P9_MISC \ + | OPTION_MASK_P9_VECTOR) \ + & ~OTHER_FUSION_MASKS) /* Support for the IEEE 128-bit floating point hardware requires a lot of the VSX instructions that are part of ISA 3.0. */ @@ -133,6 +140,7 @@ | OPTION_MASK_MODULO \ | OPTION_MASK_MULHW \ | OPTION_MASK_NO_UPDATE \ + | OPTION_MASK_P8_FUSION \ | OPTION_MASK_P8_VECTOR \ | OPTION_MASK_P9_MINMAX \ | OPTION_MASK_P9_MISC \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index d47e771f4e0..3afe78f5d04 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4040,6 +4040,41 @@ rs6000_option_override_internal (bool global_init_p) && optimize_function_for_speed_p (cfun)) rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT; + /* Enable power8 fusion if we are tuning for power8, even if we aren't + generating power8 instructions. Power9 does not optimize power8 fusion + cases. */ + if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)) + { + if (processor_target_table[tune_index].processor == PROCESSOR_POWER8) + rs6000_isa_flags |= OPTION_MASK_P8_FUSION; + else + rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION; + } + + /* Setting additional fusion flags turns on base fusion. */ + if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN) + { + if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION) + { + if (TARGET_P8_FUSION_SIGN) + error ("%qs requires %qs", "-mpower8-fusion-sign", + "-mpower8-fusion"); + + rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION; + } + else + rs6000_isa_flags |= OPTION_MASK_P8_FUSION; + } + + /* Power8 does not fuse sign extended loads with the addis. If we are + optimizing at high levels for speed, convert a sign extended load into a + zero extending load, and an explicit sign extension. */ + if (TARGET_P8_FUSION + && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN) + && optimize_function_for_speed_p (cfun) + && optimize >= 3) + rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN; + /* ISA 3.0 vector instructions include ISA 2.07. */ if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR) { @@ -23948,6 +23983,8 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "pcrel-opt", OPTION_MASK_PCREL_OPT, false, true }, { "popcntb", OPTION_MASK_POPCNTB, false, true }, { "popcntd", OPTION_MASK_POPCNTD, false, true }, + { "power8-fusion", OPTION_MASK_P8_FUSION, false, true }, + { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true }, { "power8-vector", OPTION_MASK_P8_VECTOR, false, true }, { "power9-minmax", OPTION_MASK_P9_MINMAX, false, true }, { "power9-misc", OPTION_MASK_P9_MISC, false, true }, @@ -23987,14 +24024,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = #endif { "soft-float", OPTION_MASK_SOFT_FLOAT, false, false }, { "string", 0, false, false }, - - /* Power8 fusion options were removed, but ignore using them in #pragma and - attribute target. Users may have used these options to suppress errors if - they declare an inline function to be specifically power8 and the function - was included by power9 or power10 which turned off the power8 fusion - support. */ - { "power8-fusion", 0, false, true }, - { "power8-fusion-sign", 0, false, true }, }; /* Builtin mask mapping for printing the flags. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 4ae45ff822f..17af314416c 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -504,19 +504,6 @@ extern int rs6000_vector_align[]; #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && (TARGET_P9_MINMAX || !flag_trapping_math)) -/* Power8 has special fusion operations that are enabled if we are tuning for - power8. This used to be settable with an option (-mpower8-fusion), but that - option has been removed. */ -#define TARGET_P8_FUSION (rs6000_tune == PROCESSOR_POWER8) - -/* Power8 fusion does not fuse loads with sign extends. If we are doing higher - optimization levels, split loads with sign extension to loads with zero - extension and an explicit sign extend operation, so that the zero extending - load can be fused. */ -#define TARGET_P8_FUSION_SIGN (TARGET_P8_FUSION \ - && optimize_function_for_speed_p (cfun) \ - && optimize >= 3) - /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. For now map OPTION_MASK_ back into MASK_. */ @@ -530,6 +517,7 @@ extern int rs6000_vector_align[]; #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW #define MASK_FPRND OPTION_MASK_FPRND +#define MASK_P8_FUSION OPTION_MASK_P8_FUSION #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT #define MASK_HTM OPTION_MASK_HTM #define MASK_ISEL OPTION_MASK_ISEL diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index ffb63027cce..4931d781c4e 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -474,19 +474,13 @@ Save the TOC in the prologue for indirect calls rather than inline. mvsx-timode Target RejectNegative Undocumented Ignore -# The -mpower8-fusion and -mpower8-fusion-sign options existed in the past, but -# they have been removed. -mno-power8-fusion -Target RejectNegative Undocumented Ignore - mpower8-fusion -Target RejectNegative Undocumented WarnRemoved - -mno-power8-fusion-sign -Target RejectNegative Undocumented Ignore +Target Mask(P8_FUSION) Var(rs6000_isa_flags) +Fuse certain integer operations together for better performance on power8. mpower8-fusion-sign -Target RejectNegative Undocumented WarnRemoved +Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) +Allow sign extension in fusion operations. mpower8-vector Target Mask(P8_VECTOR) Var(rs6000_isa_flags) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index cf7e4e22de6..a0fa5e1cf43 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1255,7 +1255,8 @@ See RS/6000 and PowerPC Options. -mveclibabi=@var{type} -mfriz -mno-friz @gol -mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol -msave-toc-indirect -mno-save-toc-indirect @gol --mpower8-vector -mno-power8-vector -mcrypto -mno-crypto -mhtm -mno-htm @gol +-mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol +-mcrypto -mno-crypto -mhtm -mno-htm @gol -mquad-memory -mno-quad-memory @gol -mquad-memory-atomic -mno-quad-memory-atomic @gol -mcompat-align-parm -mno-compat-align-parm @gol @@ -28079,7 +28080,7 @@ following options: -mpopcntb -mpopcntd -mpowerpc64 @gol -mpowerpc-gpopt -mpowerpc-gfxopt @gol -mmulhw -mdlmzb -mmfpgpr -mvsx @gol --mcrypto -mhtm -mpower8-vector @gol +-mcrypto -mhtm -mpower8-fusion -mpower8-vector @gol -mquad-memory -mquad-memory-atomic -mfloat128 @gol -mfloat128-hardware -mprefixed -mpcrel -mmma @gol -mrop-protect} @@ -28194,6 +28195,14 @@ Enable (disable) the use of the built-in functions that allow direct access to the Hardware Transactional Memory (HTM) instructions that were added in version 2.07 of the PowerPC ISA. +@item -mpower8-fusion +@itemx -mno-power8-fusion +@opindex mpower8-fusion +@opindex mno-power8-fusion +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. + @item -mpower8-vector @itemx -mno-power8-vector @opindex mpower8-vector diff --git a/gcc/testsuite/gcc.target/powerpc/pr102059-4.c b/gcc/testsuite/gcc.target/powerpc/pr102059-4.c deleted file mode 100644 index 5fe66f8af4b..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/pr102059-4.c +++ /dev/null @@ -1,23 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-O2 -mdejagnu-cpu=power10" } */ -/* { dg-require-effective-target power10_ok } */ - -/* Verify that power10 can explicity include functions compiled for power8. - The issue was -mcpu=power8 enables -mpower8-fusion, but -mcpu=power9 or - -mcpu=power10 do not set power8-fusion by default. Thus when doing this - compilation, they would get an error that the inline function failed in its - inlining due to having incompatible options. */ - -static inline int __attribute__ ((always_inline,target("cpu=power8"))) -foo (int *b) -{ - *b += 10; - return *b; -} - -int -bar (int *a) -{ - *a = foo (a); - return 0; -}