From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 01F4F3858D39; Fri, 11 Mar 2022 01:44:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 01F4F3858D39 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work081)] Update ChangeLog.meissner. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work081 X-Git-Oldrev: d40b6eb0bc5e409482babda5336557a5fad5cbf4 X-Git-Newrev: bd6771b43e7cf2cd3012c0694c72763dcb0a5f12 Message-Id: <20220311014434.01F4F3858D39@sourceware.org> Date: Fri, 11 Mar 2022 01:44:34 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Mar 2022 01:44:34 -0000 https://gcc.gnu.org/g:bd6771b43e7cf2cd3012c0694c72763dcb0a5f12 commit bd6771b43e7cf2cd3012c0694c72763dcb0a5f12 Author: Michael Meissner Date: Thu Mar 10 20:43:14 2022 -0500 Update ChangeLog.meissner. 2022-03-10 Michael Meissner gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 1c9b6b19bc7..4911d732a86 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,32 @@ +========== Work081, patch #4 +Fix DImode to TImode sign extend issue + +PR target/104868 had had an issue where my code that updated the DImode to +TImode sign extension for power10 failed. In looking at the failure +message, the reason is when extendditi2 tries to split the insn, it +generates an insn that does not satisfy its constraints: + + (set (reg:V2DI 65 1) + (vec_duplicate:V2DI (reg:DI 0))) + +The reason is vsx_splat_v2di does not allow GPR register 0 when the will +be generating a mtvsrdd instruction. In the definition of the mtvsrdd +instruction, if the RA register is 0, it means clear the upper 64 bits of +the vector instead of moving register GPR 0 to those bits. + +When I wrote the extendditi2 pattern, I forgot that mtvsrdd had that +behavior so I used a 'r' constraint instead of 'b'. In the rare case +where the value is in GPR register 0, this split will fail. + +This patch uses the right constraint for extendditi2. + +2022-03-10 Michael Meissner + +gcc/ + PR target/104868 + * config/rs6000/vsx.md (extendditi2): Use a 'b' constraint when + moving from a GPR register to an Altivec register. + ========== Work081, patch #3 Make power8-fusion depend only on tuning for power8.