From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1251) id BFAC83857820; Fri, 11 Mar 2022 17:59:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BFAC83857820 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Roger Sayle To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-7616] PR tree-optimization/98335: New peephole2 xorl; movb -> movzbl X-Act-Checkin: gcc X-Git-Author: Roger Sayle X-Git-Refname: refs/heads/master X-Git-Oldrev: c5288df751f9ecd11898dec5f2a7b6b03267f79e X-Git-Newrev: 251ea6dfbdb4448875e41081682bb3aa451b5729 Message-Id: <20220311175951.BFAC83857820@sourceware.org> Date: Fri, 11 Mar 2022 17:59:51 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Mar 2022 17:59:51 -0000 https://gcc.gnu.org/g:251ea6dfbdb4448875e41081682bb3aa451b5729 commit r12-7616-g251ea6dfbdb4448875e41081682bb3aa451b5729 Author: Roger Sayle Date: Fri Mar 11 17:57:12 2022 +0000 PR tree-optimization/98335: New peephole2 xorl;movb -> movzbl This patch is the backend piece of my proposed fix to PR tree-opt/98335, to allow C++ partial struct initialization to be as efficient/optimized as full struct initialization. With the middle-end patch just posted to gcc-patches, the test case in the PR compiles on x86_64-pc-linux-gnu with -O2 to: xorl %eax, %eax movb c(%rip), %al ret with this additional peephole2 (actually four peephole2s): movzbl c(%rip), %eax ret 2022-03-11 Roger Sayle gcc/ChangeLog PR tree-optimization/98335 * config/i386/i386.md (peephole2): Eliminate redundant insv. Combine movl followed by movb. Transform xorl followed by a suitable movb or movw into the equivalent movz[bw]l. gcc/testsuite/ChangeLog PR tree-optimization/98335 * g++.target/i386/pr98335.C: New test case. * gcc.target/i386/pr98335.c: New test case. Diff: --- gcc/config/i386/i386.md | 50 +++++++++++++++++++++++++++++++++ gcc/testsuite/g++.target/i386/pr98335.C | 18 ++++++++++++ gcc/testsuite/gcc.target/i386/pr98335.c | 12 ++++++++ 3 files changed, 80 insertions(+) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d15170e8acf..c8fbf605e41 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -3180,6 +3180,38 @@ (const_int 8)) (subreg:SWI248 (match_dup 1) 0))]) +;; Eliminate redundant insv, e.g. xorl %eax,%eax; movb $0, %ah +(define_peephole2 + [(parallel [(set (match_operand:SWI48 0 "general_reg_operand") + (const_int 0)) + (clobber (reg:CC FLAGS_REG))]) + (set (zero_extract:SWI248 (match_operand:SWI248 1 "general_reg_operand") + (const_int 8) + (const_int 8)) + (const_int 0))] + "REGNO (operands[0]) == REGNO (operands[1])" + [(parallel [(set (match_operand:SWI48 0 "general_reg_operand") + (const_int 0)) + (clobber (reg:CC FLAGS_REG))])]) + +;; Combine movl followed by movb. +(define_peephole2 + [(set (match_operand:SWI48 0 "general_reg_operand") + (match_operand:SWI48 1 "const_int_operand")) + (set (zero_extract:SWI248 (match_operand:SWI248 2 "general_reg_operand") + (const_int 8) + (const_int 8)) + (match_operand:SWI248 3 "const_int_operand"))] + "REGNO (operands[0]) == REGNO (operands[2])" + [(set (match_operand:SWI48 0 "general_reg_operand") + (match_dup 4))] +{ + HOST_WIDE_INT tmp = INTVAL (operands[1]) & ~(HOST_WIDE_INT)0xff00; + tmp |= (INTVAL (operands[3]) & 0xff) << 8; + operands[4] = gen_int_mode (tmp, mode); +}) + + (define_code_iterator any_extract [sign_extract zero_extract]) (define_insn "*insvqi_2" @@ -4276,6 +4308,24 @@ [(set_attr "isa" "*,avx512dq,avx512dq") (set_attr "type" "imovx,mskmov,mskmov") (set_attr "mode" "SI,QI,QI")]) + +;; Transform xorl; mov[bw] (set strict_low_part) into movz[bw]l. +(define_peephole2 + [(parallel [(set (match_operand:SWI48 0 "general_reg_operand") + (const_int 0)) + (clobber (reg:CC FLAGS_REG))]) + (set (strict_low_part (match_operand:SWI12 1 "general_reg_operand")) + (match_operand:SWI12 2 "nonimmediate_operand"))] + "REGNO (operands[0]) == REGNO (operands[1])" + [(set (match_dup 0) (zero_extend:SWI48 (match_dup 2)))]) + +;; Likewise, but preserving FLAGS_REG. +(define_peephole2 + [(set (match_operand:SWI48 0 "general_reg_operand") (const_int 0)) + (set (strict_low_part (match_operand:SWI12 1 "general_reg_operand")) + (match_operand:SWI12 2 "nonimmediate_operand"))] + "REGNO (operands[0]) == REGNO (operands[1])" + [(set (match_dup 0) (zero_extend:SWI48 (match_dup 2)))]) ;; Sign extension instructions diff --git a/gcc/testsuite/g++.target/i386/pr98335.C b/gcc/testsuite/g++.target/i386/pr98335.C new file mode 100644 index 00000000000..2581b83ab6a --- /dev/null +++ b/gcc/testsuite/g++.target/i386/pr98335.C @@ -0,0 +1,18 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +struct Data { + char a; + int b; +}; + +char c; + +Data val(int idx) { + return { c }; // { dg-warning "extended initializer" "c++ 98" { target { c++98_only } } } +} + +/* { dg-final { scan-assembler "movzbl" } } */ +/* { dg-final { scan-assembler-not "xorl" } } */ +/* { dg-final { scan-assembler-not "movb" } } */ + diff --git a/gcc/testsuite/gcc.target/i386/pr98335.c b/gcc/testsuite/gcc.target/i386/pr98335.c new file mode 100644 index 00000000000..7fa7ad70dce --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98335.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +union Data { char a; short b; }; + +char c; + +void val(void) { + __asm__ __volatile__ ("" : : "r" ((union Data) { c } )); } + +/* { dg-final { scan-assembler "movzbl" } } */ +/* { dg-final { scan-assembler-not "xorl" } } */ +/* { dg-final { scan-assembler-not "movb" } } */