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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work081)] Allow extendditi2 on power9 Date: Fri, 11 Mar 2022 20:12:12 +0000 (GMT) [thread overview] Message-ID: <20220311201212.650553858D3C@sourceware.org> (raw) https://gcc.gnu.org/g:cdfe0ccc4e67643d3a05f303cdbdea339adc7cdc commit cdfe0ccc4e67643d3a05f303cdbdea339adc7cdc Author: Michael Meissner <meissner@linux.ibm.com> Date: Fri Mar 11 15:11:56 2022 -0500 Allow extendditi2 on power9 2022-03-11 Michael Meissner <meissner@linux.ibm.com> gcc/ PR target/103109 * config/rs6000/vsx.md (extendditi2): Allow extendidti2 to run on a power9 system. Diff: --- gcc/config/rs6000/vsx.md | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 15bd86dfdfb..7cefd9388fb 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5031,11 +5031,14 @@ ;; ;; If the register allocator prefers to use Altivec registers on power10, ;; generate the vextsd2q instruction. +;; +;; We also need the GPR code for power9 so that we can optimize to use the +;; multiply-add instructions. (define_insn_and_split "extendditi2" [(set (match_operand:TI 0 "register_operand" "=r,r,v,v,v") (sign_extend:TI (match_operand:DI 1 "input_operand" "r,m,b,wa,Z"))) (clobber (reg:DI CA_REGNO))] - "TARGET_POWERPC64 && TARGET_POWER10" + "TARGET_POWERPC64 && TARGET_MADDLD" "#" "&& reload_completed" [(pc)] @@ -5082,7 +5085,8 @@ gcc_unreachable (); } [(set_attr "length" "8") - (set_attr "type" "shift,load,vecmove,vecperm,load")]) + (set_attr "type" "shift,load,vecmove,vecperm,load") + (set_attr "isa" "p9,p9,p10,p10,p10")]) ;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg (define_insn "extendditi2_vector"
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