From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 508413858019; Tue, 15 Mar 2022 21:47:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 508413858019 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work081)] Add zero_extendditi2. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work081 X-Git-Oldrev: fad5716a6579578052024626445b6a645a1c8a76 X-Git-Newrev: 257c0baeaf1280a4f6e6ecb137d38151176f17a8 Message-Id: <20220315214702.508413858019@sourceware.org> Date: Tue, 15 Mar 2022 21:47:02 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Mar 2022 21:47:02 -0000 https://gcc.gnu.org/g:257c0baeaf1280a4f6e6ecb137d38151176f17a8 commit 257c0baeaf1280a4f6e6ecb137d38151176f17a8 Author: Michael Meissner Date: Tue Mar 15 17:46:41 2022 -0400 Add zero_extendditi2. 2022-03-15 Michael Meissner gcc/ * config/rs6000/vsx.md (zero_extendditi2): New insn. Diff: --- gcc/config/rs6000/vsx.md | 55 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 2fab6843c5f..c6dc01e55e3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5121,6 +5121,61 @@ "vextsd2q %0,%1" [(set_attr "type" "vecexts")]) +;; Zero extend DImode to TImode when the result is in GPRs or VSX registers. +;; If we are on a power10, the combiner will create the lxvrdx pattern if +;; the value is being loaded from memory. +(define_insn_and_split "zero_extendditi2" + [(set (match_operand:TI 0 "gpc_reg_operand" "=r, r, wa, wa") + (zero_extend:TI + (match_operand:DI 1 "gpc_reg_operand" "r, wa, r, wa"))) + (clobber (match_scratch:DI 2 "=X, X, X, &wa"))] + "TARGET_POWERPC64 && TARGET_P9_VECTOR" + "@ + # + # + mtvsrdd %x0,0,%1 + #" + "&& reload_completed + && (int_reg_operand (operands[0], TImode) + || vsx_register_operand (operands[1], DImode))" + [(pc)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + int dest_regno = reg_or_subregno (dest); + + /* Handle conversion to GPR registers. Load up the low part and then load + 0 to clear the upper part. */ + if (INT_REGNO_P (dest_regno)) + { + rtx dest_hi = gen_highpart (DImode, dest); + rtx dest_lo = gen_lowpart (DImode, dest); + + emit_move_insn (dest_lo, src); + emit_move_insn (dest_hi, const0_rtx); + DONE; + } + + /* For conversion to a VSX register from a VSX register, do a CONCAT + operation with the upper word set to 0. */ + else if (VSX_REGNO_P (dest_regno)) + { + rtx tmp = operands[2]; + rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno); + + emit_move_insn (tmp, const0_rtx); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_concat_v2di (dest_v2di, tmp, src)); + else + emit_insn (gen_vsx_concat_v2di (dest_v2di, src, tmp)); + DONE; + } + + else + gcc_unreachable (); +} + [(set_attr "length" "8,8,*,8") + (set_attr "type" "*,mfvsr,mtvsr,vecperm")]) ;; ISA 3.0 Binary Floating-Point Support