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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work082)] Add zero_extendditi2 for power9. Date: Fri, 18 Mar 2022 18:45:51 +0000 (GMT) [thread overview] Message-ID: <20220318184551.04C72388451F@sourceware.org> (raw) https://gcc.gnu.org/g:cfa0de2afeae2779fde477b6a6bf6fd6f171a307 commit cfa0de2afeae2779fde477b6a6bf6fd6f171a307 Author: Michael Meissner <meissner@linux.ibm.com> Date: Fri Mar 18 14:45:33 2022 -0400 Add zero_extendditi2 for power9. This patch provides a zero_extendditi2 pattern for power9 and power10. On power8 and previous systems, the generic machine indepenent code will be used. This patch will be a building block to support in a future patch PR target/103109 which wants to optimize 128-bit some integer multiply-add combinations to use the power9 maddld, maddhd, maddhdu instructions. 2022-03-18 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/vsx.md (zero_extendditi2): New insn. Diff: --- gcc/config/rs6000/vsx.md | 55 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 2fab6843c5f..c6dc01e55e3 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5121,6 +5121,61 @@ "vextsd2q %0,%1" [(set_attr "type" "vecexts")]) +;; Zero extend DImode to TImode when the result is in GPRs or VSX registers. +;; If we are on a power10, the combiner will create the lxvrdx pattern if +;; the value is being loaded from memory. +(define_insn_and_split "zero_extendditi2" + [(set (match_operand:TI 0 "gpc_reg_operand" "=r, r, wa, wa") + (zero_extend:TI + (match_operand:DI 1 "gpc_reg_operand" "r, wa, r, wa"))) + (clobber (match_scratch:DI 2 "=X, X, X, &wa"))] + "TARGET_POWERPC64 && TARGET_P9_VECTOR" + "@ + # + # + mtvsrdd %x0,0,%1 + #" + "&& reload_completed + && (int_reg_operand (operands[0], TImode) + || vsx_register_operand (operands[1], DImode))" + [(pc)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + int dest_regno = reg_or_subregno (dest); + + /* Handle conversion to GPR registers. Load up the low part and then load + 0 to clear the upper part. */ + if (INT_REGNO_P (dest_regno)) + { + rtx dest_hi = gen_highpart (DImode, dest); + rtx dest_lo = gen_lowpart (DImode, dest); + + emit_move_insn (dest_lo, src); + emit_move_insn (dest_hi, const0_rtx); + DONE; + } + + /* For conversion to a VSX register from a VSX register, do a CONCAT + operation with the upper word set to 0. */ + else if (VSX_REGNO_P (dest_regno)) + { + rtx tmp = operands[2]; + rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno); + + emit_move_insn (tmp, const0_rtx); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_concat_v2di (dest_v2di, tmp, src)); + else + emit_insn (gen_vsx_concat_v2di (dest_v2di, src, tmp)); + DONE; + } + + else + gcc_unreachable (); +} + [(set_attr "length" "8,8,*,8") + (set_attr "type" "*,mfvsr,mtvsr,vecperm")]) \f ;; ISA 3.0 Binary Floating-Point Support
next reply other threads:[~2022-03-18 18:45 UTC|newest] Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-18 18:45 Michael Meissner [this message] 2022-03-22 17:40 Michael Meissner
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