From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 64F8E3858401; Wed, 23 Mar 2022 01:29:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 64F8E3858401 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work082 X-Git-Oldrev: 04202834321f47425cea3b86c6b4477c8b5eea03 X-Git-Newrev: 107cdf9c04e9b81539aa7661bcdae63afa671c1d Message-Id: <20220323012913.64F8E3858401@sourceware.org> Date: Wed, 23 Mar 2022 01:29:13 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Mar 2022 01:29:13 -0000 https://gcc.gnu.org/g:107cdf9c04e9b81539aa7661bcdae63afa671c1d commit 107cdf9c04e9b81539aa7661bcdae63afa671c1d Author: Michael Meissner Date: Tue Mar 22 21:28:53 2022 -0400 Update ChangeLog.meissner. 2022-03-22 Michael Meissner gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index c79a5a5e387..53691a0dc53 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,20 @@ +==================== Work082, patch #5: +Generate vadduqm and vsubuqm for TImode add/subtract + +If the TImode variable is in an Altivec register instead of a GPR +register, then generate vadduqm and vsubuqm instead of having to move the +value to the GPR registers and doing the add and subtract with carry +instructions. To do this, we have to delay the splitting of the addition +and subtraction until after register allocation. + +2022-03-22 Michael Meissner + +gcc/ + * config/rs6000/rs6000.md (addti3): Generate vadduqm if we are + using the Altivec registers. + (subti3): Generate vsubuqm if we using the Altivec registers. + (negti3): New insn. + ==================== Work082, patch #4: Optimize multiply/add of DImode extended to TImode. @@ -47,10 +64,10 @@ instructions. In order to support recognizing the multiply and add combination, we need to keep the addti3 and subti3 as complete insns through the combiner phase. -2022-03-18 Michael Meissner +2022-03-22 Michael Meissner gcc/ - * config/rs6000/rs6000.md (addti3): Don't immediate expand the + * config/rs6000/rs6000.md (addti3): Don't immediately expand the insn, delay expansion until the split passes. (subti3): Likewise.