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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work082)] Improve vsx_extract_<mode> Date: Wed, 23 Mar 2022 23:32:24 +0000 (GMT) [thread overview] Message-ID: <20220323233224.BEE4E3858C2C@sourceware.org> (raw) https://gcc.gnu.org/g:dccdb5e79c21b11a6a2080ec91ae69a3d6a183d3 commit dccdb5e79c21b11a6a2080ec91ae69a3d6a183d3 Author: Michael Meissner <meissner@linux.ibm.com> Date: Wed Mar 23 19:32:02 2022 -0400 Improve vsx_extract_<mode> In looking at PR target/99293, I noticed that the code in vsx_extract_<mode> could be improved. When the element being extracted is the element in the upper 64-bits, we should do an insn_split to convert this to a simple move. This would allow the post reload passes to eliminate the move completely. The insn type attribute was incorrect in that it used "mfvsr" instead of "vecperm" when a xxpermdi would be generated. Also, when a "mvfsrld" would be generated, the type should be "mfvsr". 2022-03-23 Michael Meissner <meissner@linux.ibm.com> gcc/ PR target/99392 * config/rs6000/rs6000.md (vsx_extract_<mode>): Split extracts that are just a move to being a move insn. Use the correct insn type for the alternatives. (insn splitter for vsx_extract_<mode>): Add new splitter. Diff: --- gcc/config/rs6000/vsx.md | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 75b85409cd8..a3e6e324d33 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3417,23 +3417,7 @@ gcc_assert (VSX_REGNO_P (op1_regno)); if (element == VECTOR_ELEMENT_SCALAR_64BIT) - { - if (op0_regno == op1_regno) - return ASM_COMMENT_START " vec_extract to same register"; - - else if (INT_REGNO_P (op0_regno) && TARGET_DIRECT_MOVE - && TARGET_POWERPC64) - return "mfvsrd %0,%x1"; - - else if (FP_REGNO_P (op0_regno) && FP_REGNO_P (op1_regno)) - return "fmr %0,%1"; - - else if (VSX_REGNO_P (op0_regno)) - return "xxlor %x0,%x1,%x1"; - - else - gcc_unreachable (); - } + return "#"; else if (element == VECTOR_ELEMENT_MFVSRLD_64BIT && INT_REGNO_P (op0_regno) && TARGET_P9_VECTOR && TARGET_POWERPC64 && TARGET_DIRECT_MOVE) @@ -3451,9 +3435,21 @@ else gcc_unreachable (); } - [(set_attr "type" "veclogical,mfvsr,mfvsr,vecperm") + [(set_attr "type" "vecsimple,vecperm,mfvsr,mfvsr") (set_attr "isa" "*,*,p8v,p9v")]) +;; Convert extracting the element in the upper 64-bit bits to just a move. +(define_split + [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand") + (vec_select:<VS_scalar> + (match_operand:VSX_D 1 "gpc_reg_operand") + (parallel [(match_operand:QI 2 "vsx_scalar_64bit")])))] + "VECTOR_MEM_VSX_P (<MODE>mode) && reload_completed" + [(set (match_dup 0) (match_dup 3))] +{ + operands[3] = gen_rtx_REG (<VS_scalar>mode, reg_or_subregno (operands[1])); +}) + ;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load" [(set (match_operand:<VS_scalar> 0 "register_operand" "=wa,wr")
next reply other threads:[~2022-03-23 23:32 UTC|newest] Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-23 23:32 Michael Meissner [this message] -- strict thread matches above, loose matches on Subject: below -- 2022-03-24 16:51 Michael Meissner 2022-03-23 16:45 Michael Meissner
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