[gcc(refs/users/meissner/heads/work082)] Revert patch.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:2f61e4c25937b132841aa3eb6c71d7f4f53b09be

commit 2f61e4c25937b132841aa3eb6c71d7f4f53b09be
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Mar 23 21:33:53 2022 -0400

    Revert patch.
    
    2022-03-23   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            PR target/99392
            Revert patch.
            * config/rs6000/rs6000.md (vsx_extract_<mode>): Split extracts
            that are just a move to being a move insn.  Use the correct insn
            type for the alternatives.
            (insn splitter for vsx_extract_<mode>): Add new splitter.

Diff:
---
 gcc/config/rs6000/vsx.md | 32 ++++++++++++++++++--------------
 1 file changed, 18 insertions(+), 14 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a3e6e324d33..75b85409cd8 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3417,7 +3417,23 @@
   gcc_assert (VSX_REGNO_P (op1_regno));
 
   if (element == VECTOR_ELEMENT_SCALAR_64BIT)
-    return "#";
+    {
+      if (op0_regno == op1_regno)
+	return ASM_COMMENT_START " vec_extract to same register";
+
+      else if (INT_REGNO_P (op0_regno) && TARGET_DIRECT_MOVE
+	       && TARGET_POWERPC64)
+	return "mfvsrd %0,%x1";
+
+      else if (FP_REGNO_P (op0_regno) && FP_REGNO_P (op1_regno))
+	return "fmr %0,%1";
+
+      else if (VSX_REGNO_P (op0_regno))
+	return "xxlor %x0,%x1,%x1";
+
+      else
+	gcc_unreachable ();
+    }
 
   else if (element == VECTOR_ELEMENT_MFVSRLD_64BIT && INT_REGNO_P (op0_regno)
 	   && TARGET_P9_VECTOR && TARGET_POWERPC64 && TARGET_DIRECT_MOVE)
@@ -3435,21 +3451,9 @@
   else
     gcc_unreachable ();
 }
-  [(set_attr "type" "vecsimple,vecperm,mfvsr,mfvsr")
+  [(set_attr "type" "veclogical,mfvsr,mfvsr,vecperm")
    (set_attr "isa" "*,*,p8v,p9v")])
 
-;; Convert extracting the element in the upper 64-bit bits to just a move.
-(define_split
-  [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand")
-	(vec_select:<VS_scalar>
-	 (match_operand:VSX_D 1 "gpc_reg_operand")
-	 (parallel [(match_operand:QI 2 "vsx_scalar_64bit")])))]
-  "VECTOR_MEM_VSX_P (<MODE>mode) && reload_completed"
-  [(set (match_dup 0) (match_dup 3))]
-{
-  operands[3] = gen_rtx_REG (<VS_scalar>mode, reg_or_subregno (operands[1]));
-})
-
 ;; Optimize extracting a single scalar element from memory.
 (define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load"
   [(set (match_operand:<VS_scalar> 0 "register_operand" "=wa,wr")