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From: Michael Meissner <meissner@gcc.gnu.org>
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Subject: [gcc(refs/users/meissner/heads/work082)] Update ChangeLog.meissner.
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https://gcc.gnu.org/g:cd5e86a0662bea0d9632c3bc9524a2e92bf0a232

commit cd5e86a0662bea0d9632c3bc9524a2e92bf0a232
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 24 14:24:36 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-24   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index bcf384fdf41..6b50a1daeb2 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,20 @@
+==================== Work082, patch #11:
+Allow vsx_extract_<mode> to use Altivec registers
+
+In looking at PR target/99293, I noticed that the vsx_extract_<mode>
+pattern for V2DImode and V2DFmode only allowed traditional floating point
+registers, and it did not allow Altivec registers.  The original code was
+written a few years ago when we used the old register allocator, and
+support for scalar floating point in Altivec registers was just being
+added to GCC.
+
+2022-03-24   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	PR target/99392
+	* config/rs6000/rs6000.md (vsx_extract_<mode>): Allow destination
+	to be an Altivec register.
+
 ==================== Work082, patch #10:
 Improve vsx_extract_<mode>