From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id C06B33858D3C; Thu, 24 Mar 2022 19:42:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C06B33858D3C Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work083)] Allow vsx_extract_ to use Altivec registers X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work083 X-Git-Oldrev: cba5bcdfb9016c02f3d9f516329339e9398405b2 X-Git-Newrev: 66046ec2e26673fe494e6a3290d46dd74b79af77 Message-Id: <20220324194255.C06B33858D3C@sourceware.org> Date: Thu, 24 Mar 2022 19:42:55 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Mar 2022 19:42:55 -0000 https://gcc.gnu.org/g:66046ec2e26673fe494e6a3290d46dd74b79af77 commit 66046ec2e26673fe494e6a3290d46dd74b79af77 Author: Michael Meissner Date: Thu Mar 24 15:42:37 2022 -0400 Allow vsx_extract_ to use Altivec registers In looking at PR target/99293, I noticed that the vsx_extract_ pattern for V2DImode and V2DFmode only allowed traditional floating point registers, and it did not allow Altivec registers. The original code was written a few years ago when we used the old register allocator, and support for scalar floating point in Altivec registers was just being added to GCC. 2022-03-24 Michael Meissner gcc/ PR target/99392 * config/rs6000/rs6000.md (vsx_extract_): Allow destination to be an Altivec register. Diff: --- gcc/config/rs6000/vsx.md | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index c79d796a513..844cca7c369 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3397,15 +3397,12 @@ ;; Optimize cases were we can do a simple or direct move. ;; Or see if we can avoid doing the move at all -;; There are some unresolved problems with reload that show up if an Altivec -;; register was picked. Limit the scalar value to FPRs for now. - (define_insn "vsx_extract_" - [(set (match_operand: 0 "gpc_reg_operand" "=d, d, wr, wr") + [(set (match_operand: 0 "gpc_reg_operand" "=wa, wa, wr, wr") (vec_select: - (match_operand:VSX_D 1 "gpc_reg_operand" "wa, wa, wa, wa") + (match_operand:VSX_D 1 "gpc_reg_operand" "wa, wa, wa, wa") (parallel - [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))] + [(match_operand:QI 2 "const_0_to_1_operand" "wD, n, wD, n")])))] "VECTOR_MEM_VSX_P (mode)" { int element = INTVAL (operands[2]);