From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 94AE03858D3C; Thu, 24 Mar 2022 19:45:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 94AE03858D3C Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work083)] Update ChangeLog.meissner. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work083 X-Git-Oldrev: 66046ec2e26673fe494e6a3290d46dd74b79af77 X-Git-Newrev: e680afadd24f8cdde94a2c34166496eabc0b8db6 Message-Id: <20220324194526.94AE03858D3C@sourceware.org> Date: Thu, 24 Mar 2022 19:45:26 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Mar 2022 19:45:26 -0000 https://gcc.gnu.org/g:e680afadd24f8cdde94a2c34166496eabc0b8db6 commit e680afadd24f8cdde94a2c34166496eabc0b8db6 Author: Michael Meissner Date: Thu Mar 24 15:45:07 2022 -0400 Update ChangeLog.meissner. 2022-03-24 Michael Meissner gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 108 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index e72802074b6..45880d06766 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,111 @@ +==================== Work083, patch #4: + +Allow vsx_extract_ to use Altivec registers + +In looking at PR target/99293, I noticed that the vsx_extract_ +pattern for V2DImode and V2DFmode only allowed traditional floating point +registers, and it did not allow Altivec registers. The original code was +written a few years ago when we used the old register allocator, and +support for scalar floating point in Altivec registers was just being +added to GCC. + +2022-03-24 Michael Meissner + +gcc/ + PR target/99392 + * config/rs6000/rs6000.md (vsx_extract_): Allow destination + to be an Altivec register. + +==================== Work083, patch #1: + +Make vsx_extract_ use correct insn attributes. + +In looking at PR target/99293, I noticed that the insn "type" attribute is +incorrect for the vsx_extract_ insns. In particular: + + 1) Simple vector register move should be vecsimple (alternative 1); + 2) Xxpermdi should be vecperm (alternative 2); (and) + 3) Mfvsrld should be mfvsr (alternative 4). + +This patch fixes those attributes. + +2022-03-24 Michael Meissner + +gcc/ + PR target/99392 + * config/rs6000/rs6000.md (vsx_extract_): Use the correct + insn type for the alternatives. + +==================== Work083, patch #1: + +Make vsx_splat__reg use correct insn attributes. + +In looking at PR target/99293, I noticed that the code in +vsx_splat__reg used "vecmove" as the "type" insn attribute when the +"mtvsrdd" is generated. It should use "mfvsr". I also added a "p9v" isa +attribute for that alternative. + +2022-03-23 Michael Meissner + +gcc/ + PR target/99392 + * config/rs6000/rs6000.md (vsx_splat__reg): Use the correct + insn type attribute. Add "p9v" isa attribute for generating the + mtvsrdd instruction. + +==================== Work083, patch #1: + +Optimize vec_splats of constant vec_extract for V2DI/V2DF. + +In PR target/99293, it was pointed out that doing: + + vector long long dest0, dest1, src; + /* ... */ + dest0 = vec_splats (vec_extract (src, 0)); + dest1 = vec_splats (vec_extract (src, 1)); + +would generate slower code. + +It generates the following code on power8: + + ;; vec_splats (vec_extract (src, 0)) + xxpermdi 0,34,34,3 + xxpermdi 34,0,0,0 + + ;; vec_splats (vec_extract (src, 1)) + xxlor 0,34,34 + xxpermdi 34,0,0,0 + +However on power9 and power10 it generates: + + ;; vec_splats (vec_extract (src, 0)) + mfvsld 3,34 + mtvsrdd 34,9,9 + + ;; vec_splats (vec_extract (src, 1)) + mfvsrd 9,34 + mtvsrdd 34,9,9 + +This is due to the power9 having the mfvsrld instruction which can extract +either 64-bit element into a GPR. + +However in this case, it is better to have a single combiner pattern that +can generate a single xxpermdi, instead of doing 2 insnsns (the extract +and then the concat). + +2022-03-24 Michael Meissner + +gcc/ + PR target/99392 + * config/rs6000/vsx.md (vsx_splat_const_extract_): New + combiner insn. + +gcc/testsuite: + PR target/99392 + * gcc.target/powerpc/pr99293.c: New test. + +==================== Baseline + 2022-03-24 Michael Meissner Clone branch