From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1039) id 9B1A03858D28; Sat, 26 Mar 2022 20:02:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9B1A03858D28 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: H.J. Lu To: gcc-cvs@gcc.gnu.org Subject: [gcc r11-9694] x86: Use x constraint on SSSE3 patterns with MMX operands X-Act-Checkin: gcc X-Git-Author: H.J. Lu X-Git-Refname: refs/heads/releases/gcc-11 X-Git-Oldrev: 23852920316ea12ff1c5f215474e627c3d22d976 X-Git-Newrev: ee25401b10a1ca6157c0a02f49f47e7b253af123 Message-Id: <20220326200255.9B1A03858D28@sourceware.org> Date: Sat, 26 Mar 2022 20:02:55 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 26 Mar 2022 20:02:55 -0000 https://gcc.gnu.org/g:ee25401b10a1ca6157c0a02f49f47e7b253af123 commit r11-9694-gee25401b10a1ca6157c0a02f49f47e7b253af123 Author: H.J. Lu Date: Thu Mar 24 21:41:12 2022 -0700 x86: Use x constraint on SSSE3 patterns with MMX operands Since PHADDW/PHADDD/PHADDSW/PHSUBW/PHSUBD/PHSUBSW/PSIGNB/PSIGNW/PSIGND have no AVX512 version, replace the "Yv" register constraint with the "x" register constraint. PR target/105052 * config/i386/sse.md (ssse3_phwv4hi3): Replace "Yv" with "x". (ssse3_phdv2si3): Likewise. (ssse3_psign3): Likewise. (cherry picked from commit 99591cf43fc1da0fb72b3da02ba937ba30bd2bf2) Diff: --- gcc/config/i386/sse.md | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 03975f92426..8f044c48b3b 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16635,12 +16635,12 @@ (set_attr "mode" "TI")]) (define_insn_and_split "ssse3_phwv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,x") (ssse3_plusminus:V4HI (vec_select:V4HI (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "0,0,Yv") - (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")) + (match_operand:V4HI 1 "register_operand" "0,0,x") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,x")) (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])) (vec_select:V4HI @@ -16722,12 +16722,12 @@ (set_attr "mode" "TI")]) (define_insn_and_split "ssse3_phdv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv") + [(set (match_operand:V2SI 0 "register_operand" "=y,x,x") (plusminus:V2SI (vec_select:V2SI (vec_concat:V4SI - (match_operand:V2SI 1 "register_operand" "0,0,Yv") - (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")) + (match_operand:V2SI 1 "register_operand" "0,0,x") + (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,x")) (parallel [(const_int 0) (const_int 2)])) (vec_select:V2SI (vec_concat:V4SI (match_dup 1) (match_dup 2)) @@ -17186,10 +17186,10 @@ (set_attr "mode" "")]) (define_insn "ssse3_psign3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x") (unspec:MMXMODEI - [(match_operand:MMXMODEI 1 "register_operand" "0,0,Yv") - (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")] + [(match_operand:MMXMODEI 1 "register_operand" "0,0,x") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")] UNSPEC_PSIGN))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" "@