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From: H.J. Lu <hjl@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r10-10514] x86: Use x constraint on SSSE3 patterns with MMX operands
Date: Sat, 26 Mar 2022 20:03:22 +0000 (GMT) [thread overview]
Message-ID: <20220326200322.60AB5385E44F@sourceware.org> (raw)
https://gcc.gnu.org/g:40e7524ada2f09ec80d8083b9608a10ed516d8fe
commit r10-10514-g40e7524ada2f09ec80d8083b9608a10ed516d8fe
Author: H.J. Lu <hjl.tools@gmail.com>
Date: Thu Mar 24 21:41:12 2022 -0700
x86: Use x constraint on SSSE3 patterns with MMX operands
Since PHADDW/PHADDD/PHADDSW/PHSUBW/PHSUBD/PHSUBSW/PSIGNB/PSIGNW/PSIGND
have no AVX512 version, replace the "Yv" register constraint with the
"x" register constraint.
PR target/105052
* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3):
Replace "Yv" with "x".
(ssse3_ph<plusminus_mnemonic>dv2si3): Likewise.
(ssse3_psign<mode>3): Likewise.
(cherry picked from commit 99591cf43fc1da0fb72b3da02ba937ba30bd2bf2)
Diff:
---
gcc/config/i386/sse.md | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 1292126a46d..90b6bf605b4 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16140,12 +16140,12 @@
(set_attr "mode" "TI")])
(define_insn_and_split "ssse3_ph<plusminus_mnemonic>wv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
+ [(set (match_operand:V4HI 0 "register_operand" "=y,x,x")
(vec_concat:V4HI
(vec_concat:V2HI
(ssse3_plusminus:HI
(vec_select:HI
- (match_operand:V4HI 1 "register_operand" "0,0,Yv")
+ (match_operand:V4HI 1 "register_operand" "0,0,x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(ssse3_plusminus:HI
@@ -16154,7 +16154,7 @@
(vec_concat:V2HI
(ssse3_plusminus:HI
(vec_select:HI
- (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")
+ (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,x")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(ssse3_plusminus:HI
@@ -16265,16 +16265,16 @@
(set_attr "mode" "TI")])
(define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3"
- [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv")
+ [(set (match_operand:V2SI 0 "register_operand" "=y,x,x")
(vec_concat:V2SI
(plusminus:SI
(vec_select:SI
- (match_operand:V2SI 1 "register_operand" "0,0,Yv")
+ (match_operand:V2SI 1 "register_operand" "0,0,x")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
(plusminus:SI
(vec_select:SI
- (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")
+ (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,x")
(parallel [(const_int 0)]))
(vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
"(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
@@ -16727,10 +16727,10 @@
(set_attr "mode" "<sseinsnmode>")])
(define_insn "ssse3_psign<mode>3"
- [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv")
+ [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x")
(unspec:MMXMODEI
- [(match_operand:MMXMODEI 1 "register_operand" "0,0,Yv")
- (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")]
+ [(match_operand:MMXMODEI 1 "register_operand" "0,0,x")
+ (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")]
UNSPEC_PSIGN))]
"(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
"@
reply other threads:[~2022-03-26 20:03 UTC|newest]
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