From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1039) id 0794A3888C59; Mon, 28 Mar 2022 13:41:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0794A3888C59 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: H.J. Lu To: gcc-cvs@gcc.gnu.org Subject: [gcc r11-9701] x86: Use Yw constraint on *ssse3_pshufbv8qi3 X-Act-Checkin: gcc X-Git-Author: H.J. Lu X-Git-Refname: refs/heads/releases/gcc-11 X-Git-Oldrev: 40e9979cf531e6a1ca1db8804c80e40e0e71de4c X-Git-Newrev: a374915186ecab108c983a84b6afcede680100a4 Message-Id: <20220328134137.0794A3888C59@sourceware.org> Date: Mon, 28 Mar 2022 13:41:37 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 28 Mar 2022 13:41:37 -0000 https://gcc.gnu.org/g:a374915186ecab108c983a84b6afcede680100a4 commit r11-9701-ga374915186ecab108c983a84b6afcede680100a4 Author: H.J. Lu Date: Sun Mar 27 11:07:39 2022 -0700 x86: Use Yw constraint on *ssse3_pshufbv8qi3 Since AVX512VL and AVX512BW are required for AVX512 VPSHUFB, replace the "Yv" register constraint with the "Yw" register constraint. gcc/ PR target/105068 * config/i386/sse.md (*ssse3_pshufbv8qi3): Replace "Yv" with "Yw". (cherry picked from commit 08e69332881f8d28ce8b559ffba1900ae5c0d5ee) Diff: --- gcc/config/i386/sse.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 32c2036b3a2..56eb8849f36 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17133,9 +17133,9 @@ }) (define_insn_and_split "*ssse3_pshufbv8qi3" - [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv") - (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,0,Yv") - (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv") + [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yw") + (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0,0,Yw") + (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yw") (match_operand:V4SI 4 "reg_or_const_vector_operand" "i,3,3")] UNSPEC_PSHUFB))