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From: Michael Meissner <meissner@gcc.gnu.org>
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Subject: [gcc(refs/users/meissner/heads/work084)] Update ChangeLog.meissner.
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https://gcc.gnu.org/g:1aaa770e86c0ef6595f85f14245e19275e489215

commit 1aaa770e86c0ef6595f85f14245e19275e489215
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Mar 31 15:54:51 2022 -0400

    Update ChangeLog.meissner.
    
    2022-03-31   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 4633953a09f..c7e98861615 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,18 @@
+==================== Work084, patch #4:
+
+Add zero_extendditi2.
+
+This pattern adds zero_extendditi2 so that if we are extending DImode to
+TImode, and we want the result in a vector register, the compiler can
+generate MTVSRDDD.  In addition, on power10, it can generate LXVRDX if it
+is loading the value from memory and wanting to use it in a vector
+register.
+
+2022-03-31   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	* config/rs6000/vsx.md (zero_extendditi2): New insn.
+
 ==================== Work084, patch #3:
 
 Replace UNSPEC with RTL code for extendditi2.