From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id D37C13858418; Fri, 1 Apr 2022 20:15:36 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D37C13858418 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work084)] Revert patch. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work084 X-Git-Oldrev: 1aaa770e86c0ef6595f85f14245e19275e489215 X-Git-Newrev: 08fe7c705fa13e4e4f52b6dce37463ed80aa61a2 Message-Id: <20220401201536.D37C13858418@sourceware.org> Date: Fri, 1 Apr 2022 20:15:36 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Apr 2022 20:15:36 -0000 https://gcc.gnu.org/g:08fe7c705fa13e4e4f52b6dce37463ed80aa61a2 commit 08fe7c705fa13e4e4f52b6dce37463ed80aa61a2 Author: Michael Meissner Date: Fri Apr 1 16:15:05 2022 -0400 Revert patch. 2022-03-31 Michael Meissner gcc/ Revert patch. * config/rs6000/vsx.md (zero_extendditi2): New insn. Diff: --- gcc/config/rs6000/vsx.md | 52 ------------------------------------------------ 1 file changed, 52 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index cc8c80863f2..c091e5e2f47 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5019,58 +5019,6 @@ DONE; }) -;; Zero extend DI to TI. If we don't have the MTVSRDD instruction (and LXVRDX -;; in the case of power10), we use the machine independent code. If we are -;; loading up GPRs, we fall back to the old code. -(define_insn_and_split "zero_extendditi2" - [(set (match_operand:TI 0 "register_operand" "=r,r,r, wa,wa,wa") - (zero_extend:TI (match_operand:DI 1 "input_operand" "r,m,wa,r, Z, wa"))) - (clobber (match_scratch:DI 2 "=X,X,X, X, X, &wa"))] - "TARGET_POWERPC64 && TARGET_POWER10" - "@ - # - # - # - mtvsrdd %x0,0,%1 - lxvrdx %x0,%y1 - #" - "&& reload_completed - && (int_reg_operand (operands[0], TImode) - || vsx_register_operand (operands[1], DImode))" - [(pc)] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - int dest_regno = reg_or_subregno (dest); - - /* Handle conversion to GPR registers. Load up the low part and then do - a sign extension to the upper part. */ - if (INT_REGNO_P (dest_regno)) - { - rtx dest_hi = gen_highpart (DImode, dest); - rtx dest_lo = gen_lowpart (DImode, dest); - - emit_move_insn (dest_lo, src); - emit_move_insn (dest_hi, const0_rtx); - DONE; - } - - /* For settomg a VSX register from another VSX register, clear a scratch - register, and use XXPERMDI to shift the value into the lower 64-bits. */ - rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno); - rtx zero = operands[2]; - - emit_move_insn (zero, const0_rtx); - if (BYTES_BIG_ENDIAN) - emit_insn (gen_vsx_concat_v2di (dest_v2di, zero, src)); - else - emit_insn (gen_vsx_concat_v2di (dest_v2di, src, zero)); - DONE; -} - [(set_attr "type" "integer,load,mfvsr,vecmove,vecload,vecperm") - (set_attr "isa" "*, *, *, *, p10, *") - (set_attr "length" "8, 8, 8, *, *, 8")]) - ;; Sign extend DI to TI. We provide both GPR targets and Altivec targets on ;; power10. On earlier systems, the machine independent code will generate a ;; shift left to sign extend the 64-bit value to 128-bit.