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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work085)] Replace UNSPEC with RTL code for extendditi2. Date: Thu, 7 Apr 2022 20:19:26 +0000 (GMT) [thread overview] Message-ID: <20220407201926.A9BA63858C50@sourceware.org> (raw) https://gcc.gnu.org/g:2fe27fea89a31b19975fa299ff6cb7aa8adb4a79 commit 2fe27fea89a31b19975fa299ff6cb7aa8adb4a79 Author: Michael Meissner <meissner@linux.ibm.com> Date: Thu Apr 7 16:19:11 2022 -0400 Replace UNSPEC with RTL code for extendditi2. When I submitted my patch on March 12th for extendditi2, Segher wished I had removed the use of the UNSPEC for the vextsd2q instruction. This patch rewrites extendditi2_vector to use VEC_SELECT rather than UNSPEC. 2022-04-07 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/vsx.md (UNSPEC_EXTENDDITI2): Delete. (extendditi2_vector): Rewrite to use VEC_SELECT as a define_expand. (extendditi2_vector2): New insn. Diff: --- gcc/config/rs6000/vsx.md | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index a1a1ce95195..c091e5e2f47 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -358,7 +358,6 @@ UNSPEC_VSX_FIRST_MISMATCH_EOS_INDEX UNSPEC_XXGENPCV UNSPEC_MTVSBM - UNSPEC_EXTENDDITI2 UNSPEC_VCNTMB UNSPEC_VEXPAND UNSPEC_VEXTRACT @@ -5083,10 +5082,25 @@ (set_attr "type" "shift,load,vecmove,vecperm,load")]) ;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg -(define_insn "extendditi2_vector" +(define_expand "extendditi2_vector" + [(use (match_operand:TI 0 "gpc_reg_operand")) + (use (match_operand:TI 1 "gpc_reg_operand"))] + "TARGET_POWER10" +{ + rtx dest = operands[0]; + rtx src_v2di = gen_lowpart (V2DImode, operands[1]); + rtx element = GEN_INT (VECTOR_ELEMENT_SCALAR_64BIT); + + emit_insn (gen_extendditi2_vector2 (dest, src_v2di, element)); + DONE; +}) + +(define_insn "extendditi2_vector2" [(set (match_operand:TI 0 "gpc_reg_operand" "=v") - (unspec:TI [(match_operand:TI 1 "gpc_reg_operand" "v")] - UNSPEC_EXTENDDITI2))] + (sign_extend:TI + (vec_select:DI + (match_operand:V2DI 1 "gpc_reg_operand" "v") + (parallel [(match_operand 2 "vsx_scalar_64bit" "wD")]))))] "TARGET_POWER10" "vextsd2q %0,%1" [(set_attr "type" "vecexts")])
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