From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id E24B63858D1E; Mon, 11 Apr 2022 18:04:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E24B63858D1E Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work085)] Update ChangeLog.meissner. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work085 X-Git-Oldrev: 6a2149e01795ecd0881c2ab8c1adbbd7897f217a X-Git-Newrev: bbdae9310ac14e81e9e5c1898f0f50c70e24a9bb Message-Id: <20220411180433.E24B63858D1E@sourceware.org> Date: Mon, 11 Apr 2022 18:04:33 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Apr 2022 18:04:34 -0000 https://gcc.gnu.org/g:bbdae9310ac14e81e9e5c1898f0f50c70e24a9bb commit bbdae9310ac14e81e9e5c1898f0f50c70e24a9bb Author: Michael Meissner Date: Mon Apr 11 14:04:15 2022 -0400 Update ChangeLog.meissner. 2022-04-11 Michael Meissner gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 2354ed8df96..9c1e8865b25 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,53 @@ +==================== Work086, patch #6: + +Add zero_extendditi2. Improve lxvr*x code generation. + +This pattern adds zero_extendditi2 so that if we are extending DImode to +TImode, and we want the result in a vector register, the compiler can +generate MTVSRDDD. + +In addition the patterns for generating lxvr{b,h,w,d}x were tuned to allow +loading to gpr registers. This prevents needlessly doing direct moves to +get the value into the vector registers if the gpr register was already +selected. + +In updating the insn counts for two tests due to these changes, I noticed +the tests were done at -O0. I changed this so that the tests are now done +at the normal -O2 optimization level. + +2022-04-11 Michael Meissner + +gcc/ + * config/rs6000/vsx.md (vsx_lxvrx): Add support for loading to + GPR registers. + (vsx_stxvrx): Add support for storing from GPR registers. + (zero_extendditi2): New insn. + +gcc/testsuite/ + * gcc.target/powerpc/vsx-load-element-extend-int.c: Use -O2 + instead of -O0 and update insn counts. + * gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise. + * gcc.target/powerpc/zero-extend-di-ti.c: New test. + +==================== Work086, patch #5: + +Make addti3/subti3 be define_insn_and_split, instead of define_expand + +This patch makes addti3 and subti3 be define_insn_and_split instead of +define_expand. This patch will be a building block to support in a future +patch PR target/103109 which wants to optimize 128-bit some integer +multiply-add combinations to use the power9 maddld, maddhd, maddhdu +instructions. In order to support recognizing the multiply and add +combination, we need to keep the addti3 and subti3 as complete insns +through the combiner phase. + +2022-04-11 Michael Meissner + +gcc/ + * config/rs6000/rs6000.md (addti3): Don't immediately expand the + insn. Delay expansion until the split passes. + (subti3): Likewise. + ==================== Work086, patch #4: Eliminate power8 fusion options, use power8 tuning, PR target/102059