From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7861) id 4A8943857378; Fri, 15 Apr 2022 12:19:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4A8943857378 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Hongyu Wang To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-8174] i386: Correct target attribute for crc32 intrinsics X-Act-Checkin: gcc X-Git-Author: Hongyu Wang X-Git-Refname: refs/heads/master X-Git-Oldrev: e580f81d22d61153564959f08d9a6d3bcc7fd386 X-Git-Newrev: a335a94a1bf49dcb3c966af05cd68be6ee36277e Message-Id: <20220415121932.4A8943857378@sourceware.org> Date: Fri, 15 Apr 2022 12:19:32 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Apr 2022 12:19:32 -0000 https://gcc.gnu.org/g:a335a94a1bf49dcb3c966af05cd68be6ee36277e commit r12-8174-ga335a94a1bf49dcb3c966af05cd68be6ee36277e Author: Hongyu Wang Date: Fri Apr 15 10:51:06 2022 +0800 i386: Correct target attribute for crc32 intrinsics Complile _mm_crc32_u8/16/32/64 intrinsics with -mcrc32 would meet target specific option mismatch. Correct target pragma to fix. gcc/ChangeLog: * config/i386/smmintrin.h: Correct target pragma from sse4.1 and sse4.2 to crc32 for crc32 intrinsics. gcc/testsuite/ChangeLog: * gcc.target/i386/crc32-6.c: Adjust dg-error message. * gcc.target/i386/crc32-7.c: New test. Diff: --- gcc/config/i386/smmintrin.h | 25 +++++++----------------- gcc/testsuite/gcc.target/i386/crc32-6.c | 2 +- gcc/testsuite/gcc.target/i386/crc32-7.c | 34 +++++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 19 deletions(-) diff --git a/gcc/config/i386/smmintrin.h b/gcc/config/i386/smmintrin.h index b42b212300f..eb6a451c10a 100644 --- a/gcc/config/i386/smmintrin.h +++ b/gcc/config/i386/smmintrin.h @@ -810,17 +810,11 @@ _mm_cmpgt_epi64 (__m128i __X, __m128i __Y) #include -#ifndef __SSE4_1__ +#ifndef __CRC32__ #pragma GCC push_options -#pragma GCC target("sse4.1") -#define __DISABLE_SSE4_1__ -#endif /* __SSE4_1__ */ - -#ifndef __SSE4_2__ -#pragma GCC push_options -#pragma GCC target("sse4.2") -#define __DISABLE_SSE4_2__ -#endif /* __SSE4_1__ */ +#pragma GCC target("crc32") +#define __DISABLE_CRC32__ +#endif /* __CRC32__ */ /* Accumulate CRC32 (polynomial 0x11EDC6F41) value. */ extern __inline unsigned int __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -849,14 +843,9 @@ _mm_crc32_u64 (unsigned long long __C, unsigned long long __V) } #endif -#ifdef __DISABLE_SSE4_2__ -#undef __DISABLE_SSE4_2__ +#ifdef __DISABLE_CRC32__ +#undef __DISABLE_CRC32__ #pragma GCC pop_options -#endif /* __DISABLE_SSE4_2__ */ - -#ifdef __DISABLE_SSE4_1__ -#undef __DISABLE_SSE4_1__ -#pragma GCC pop_options -#endif /* __DISABLE_SSE4_1__ */ +#endif /* __DISABLE_CRC32__ */ #endif /* _SMMINTRIN_H_INCLUDED */ diff --git a/gcc/testsuite/gcc.target/i386/crc32-6.c b/gcc/testsuite/gcc.target/i386/crc32-6.c index 464e3444069..7f2b42df3a2 100644 --- a/gcc/testsuite/gcc.target/i386/crc32-6.c +++ b/gcc/testsuite/gcc.target/i386/crc32-6.c @@ -10,4 +10,4 @@ test_mm_crc32_u8 (unsigned int CRC, unsigned char V) return _mm_crc32_u8 (CRC, V); } -/* { dg-error "needs isa option -mcrc32" "" { target *-*-* } 0 } */ +/* { dg-error "target specific option mismatch" "" { target *-*-* } 0 } */ diff --git a/gcc/testsuite/gcc.target/i386/crc32-7.c b/gcc/testsuite/gcc.target/i386/crc32-7.c new file mode 100644 index 00000000000..2e310e38b82 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/crc32-7.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcrc32" } */ +/* { dg-final { scan-assembler "crc32b\[^\\n\]*eax" } } */ +/* { dg-final { scan-assembler "crc32w\[^\\n\]*eax" } } */ +/* { dg-final { scan-assembler "crc32l\[^\\n\]*eax" } } */ +/* { dg-final { scan-assembler "crc32q\[^\\n\]*rax" { target { ! ia32 } } } } */ + +#include + +unsigned int +test_mm_crc32_u8 (unsigned int CRC, unsigned char V) +{ + return _mm_crc32_u8 (CRC, V); +} + +unsigned int +test_mm_crc32_u16 (unsigned int CRC, unsigned short V) +{ + return _mm_crc32_u16 (CRC, V); +} + +unsigned int +test_mm_crc32_u32 (unsigned int CRC, unsigned int V) +{ + return _mm_crc32_u32 (CRC, V); +} + +#ifdef __x86_64__ +unsigned long long +test_mm_crc32_u64 (unsigned long long CRC, unsigned long long V) +{ + return _mm_crc32_u64 (CRC, V); +} +#endif