From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2153) id 47F6E3858D1E; Tue, 26 Apr 2022 08:12:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 47F6E3858D1E MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Jakub Jelinek To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-8264] ifcvt: Improve noce_try_store_flag_mask [PR105314] X-Act-Checkin: gcc X-Git-Author: Jakub Jelinek X-Git-Refname: refs/heads/master X-Git-Oldrev: d4836ac9acd0c991a4fe1dec9438773a2c4eb5ac X-Git-Newrev: 7d31c678d68d7b6820a958584619ca763b0eb9c5 Message-Id: <20220426081241.47F6E3858D1E@sourceware.org> Date: Tue, 26 Apr 2022 08:12:41 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Apr 2022 08:12:41 -0000 https://gcc.gnu.org/g:7d31c678d68d7b6820a958584619ca763b0eb9c5 commit r12-8264-g7d31c678d68d7b6820a958584619ca763b0eb9c5 Author: Jakub Jelinek Date: Tue Apr 26 10:11:58 2022 +0200 ifcvt: Improve noce_try_store_flag_mask [PR105314] The following testcase regressed on riscv due to the splitting of critical edges in the sink pass, similarly to x86_64 compared to GCC 11 we now swap the edges, whether true or false edge goes to an empty forwarded bb. From GIMPLE POV, those 2 forms are equivalent, but as can be seen here, for some ifcvt opts it matters one way or another. On this testcase, noce_try_store_flag_mask used to trigger and transformed if (pseudo2) pseudo1 = 0; into pseudo1 &= -(pseudo2 == 0); But with the swapped edges ifcvt actually sees if (!pseudo2) pseudo3 = pseudo1; else pseudo3 = 0; and noce_try_store_flag_mask punts. IMHO there is no reason why it should punt those, it is equivalent to pseudo3 = pseudo1 & -(pseudo2 == 0); and especially if the target has 3 operand AND, it shouldn't be any more costly (and even with 2 operand AND, it might very well happen that RA can make it happen without any extra moves). Initially I've just removed the rtx_equal_p calls from the conditions and didn't add anything there, but that broke aarch64 bootstrap and regressed some testcases on x86_64, where if_info->a or if_info->b could be some larger expression that we can't force into a register. Furthermore, the case where both if_info->a and if_info->b are constants is better handled by other ifcvt optimizations like noce_try_store_flag or noce_try_inverse_constants or noce_try_store_flag_constants. So, I've restricted it to just a REG (perhaps SUBREG of REG might be ok too) next to what has been handled previously. 2022-04-26 Jakub Jelinek PR rtl-optimization/105314 * ifcvt.cc (noce_try_store_flag_mask): Don't require that the non-zero operand is equal to if_info->x, instead use the non-zero operand as one of the operands of AND with if_info->x as target. * gcc.target/riscv/pr105314.c: New test. Diff: --- gcc/ifcvt.cc | 6 +++--- gcc/testsuite/gcc.target/riscv/pr105314.c | 12 ++++++++++++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index 22960a67f89..b983e87389f 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -1678,10 +1678,10 @@ noce_try_store_flag_mask (struct noce_if_info *if_info) reversep = 0; if ((if_info->a == const0_rtx - && rtx_equal_p (if_info->b, if_info->x)) + && (REG_P (if_info->b) || rtx_equal_p (if_info->b, if_info->x))) || ((reversep = (noce_reversed_cond_code (if_info) != UNKNOWN)) && if_info->b == const0_rtx - && rtx_equal_p (if_info->a, if_info->x))) + && (REG_P (if_info->a) || rtx_equal_p (if_info->a, if_info->x)))) { start_sequence (); target = noce_emit_store_flag (if_info, @@ -1689,7 +1689,7 @@ noce_try_store_flag_mask (struct noce_if_info *if_info) reversep, -1); if (target) target = expand_simple_binop (GET_MODE (if_info->x), AND, - if_info->x, + reversep ? if_info->a : if_info->b, target, if_info->x, 0, OPTAB_WIDEN); diff --git a/gcc/testsuite/gcc.target/riscv/pr105314.c b/gcc/testsuite/gcc.target/riscv/pr105314.c new file mode 100644 index 00000000000..7a54577e9a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr105314.c @@ -0,0 +1,12 @@ +/* PR rtl-optimization/105314 */ +/* { dg-do compile } * +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "\tbeq\t" } } */ + +long +foo (long a, long b, long c) +{ + if (c) + a = 0; + return a; +}