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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work087)] Revert patch. Date: Thu, 28 Apr 2022 21:02:59 +0000 (GMT) [thread overview] Message-ID: <20220428210259.872053858C2C@sourceware.org> (raw) https://gcc.gnu.org/g:c1f78c70ee0d7f14324af1d60c2d3b15aad2722c commit c1f78c70ee0d7f14324af1d60c2d3b15aad2722c Author: Michael Meissner <meissner@linux.ibm.com> Date: Thu Apr 28 17:01:13 2022 -0400 Revert patch. 2022-04-28 Michael Meissner <meissner@linux.ibm.com> gcc/ Revert patch. PR target/103109 * config/rs6000/rs6000.md (su_int32): New code attribute. (<u>mul<mode><dmode>3): Convert from define_expand to define_insn_and_split. (maddld<mode>4): Add generator function. (<u>mulditi3_<u>adddi3): New insn. (<u>mulditi3_add_const): New insn. (<u>mulditi3_<u>adddi3_upper): New insn. Diff: --- gcc/config/rs6000/rs6000.md | 128 +++----------------------------------------- 1 file changed, 6 insertions(+), 122 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index a78f419f5f3..c9e5b5f10e0 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -687,9 +687,6 @@ (float "") (unsigned_float "uns")]) -(define_code_attr su_int32 [(sign_extend "s32bit_cint_operand") - (zero_extend "c32bit_cint_operand")]) - ; Various instructions that come in SI and DI forms. ; A generic w/d attribute, for things like cmpw/cmpd. (define_mode_attr wd [(QI "b") @@ -3213,16 +3210,13 @@ "mulhw<u> %0,%1,%2" [(set_attr "type" "mul")]) -(define_insn_and_split "<u>mul<mode><dmode>3" - [(set (match_operand:<DMODE> 0 "gpc_reg_operand" "=&r") +(define_expand "<u>mul<mode><dmode>3" + [(set (match_operand:<DMODE> 0 "gpc_reg_operand") (mult:<DMODE> (any_extend:<DMODE> - (match_operand:GPR 1 "gpc_reg_operand" "r")) + (match_operand:GPR 1 "gpc_reg_operand")) (any_extend:<DMODE> - (match_operand:GPR 2 "gpc_reg_operand" "r"))))] + (match_operand:GPR 2 "gpc_reg_operand"))))] "!(<MODE>mode == SImode && TARGET_POWERPC64)" - "#" - "&& 1" - [(pc)] { rtx l = gen_reg_rtx (<MODE>mode); rtx h = gen_reg_rtx (<MODE>mode); @@ -3231,10 +3225,9 @@ emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l); emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h); DONE; -} - [(set_attr "length" "8")]) +}) -(define_insn "maddld<mode>4" +(define_insn "*maddld<mode>4" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (plus:GPR (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") (match_operand:GPR 2 "gpc_reg_operand" "r")) @@ -3243,115 +3236,6 @@ "maddld %0,%1,%2,%3" [(set_attr "type" "mul")]) -(define_insn_and_split "*<u>mulditi3_<u>adddi3" - [(set (match_operand:TI 0 "gpc_reg_operand" "=&r") - (plus:TI - (mult:TI - (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r")) - (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r"))) - (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r"))))] - "TARGET_MADDLD && TARGET_POWERPC64" - "#" - "&& 1" - [(pc)] -{ - rtx dest = operands[0]; - rtx dest_hi = gen_highpart (DImode, dest); - rtx dest_lo = gen_lowpart (DImode, dest); - rtx op1 = operands[1]; - rtx op2 = operands[2]; - rtx op3 = operands[3]; - rtx tmp_hi, tmp_lo; - - if (can_create_pseudo_p ()) - { - tmp_hi = gen_reg_rtx (DImode); - tmp_lo = gen_reg_rtx (DImode); - } - else - { - tmp_hi = dest_hi; - tmp_lo = dest_lo; - } - - emit_insn (gen_<u>mulditi3_<u>adddi3_upper (tmp_hi, op1, op2, op3)); - emit_insn (gen_maddlddi4 (tmp_lo, op1, op2, op3)); - - if (can_create_pseudo_p ()) - { - emit_move_insn (dest_hi, tmp_hi); - emit_move_insn (dest_lo, tmp_lo); - } - DONE; -} - [(set_attr "length" "8")]) - -;; Optimize 128-bit multiply with zero/sign extend and adding a constant. We -;; force the constant into a register to generate li, maddhd, and maddld, -;; instead of mulld, mulhd, addic, and addze. We can't combine this pattern -;; with the pattern that handles registers, since constants don't have a sign -;; or zero extend around them. -(define_insn_and_split "*<u>mulditi3_add_const" - [(set (match_operand:TI 0 "gpc_reg_operand" "=&r") - (plus:TI - (mult:TI - (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r")) - (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r"))) - (match_operand 3 "<su_int32>" "r")))] - "TARGET_MADDLD && TARGET_POWERPC64 -" - "#" - "&& 1" - [(pc)] -{ - rtx dest = operands[0]; - rtx dest_hi = gen_highpart (DImode, dest); - rtx dest_lo = gen_lowpart (DImode, dest); - rtx op1 = operands[1]; - rtx op2 = operands[2]; - rtx op3 = force_reg (DImode, operands[3]); - rtx tmp_hi, tmp_lo; - - if (can_create_pseudo_p ()) - { - tmp_hi = gen_reg_rtx (DImode); - tmp_lo = gen_reg_rtx (DImode); - } - else - { - tmp_hi = dest_hi; - tmp_lo = dest_lo; - } - - emit_insn (gen_<u>mulditi3_<u>adddi3_upper (tmp_hi, op1, op2, op3)); - emit_insn (gen_maddlddi4 (tmp_lo, op1, op2, op3)); - - if (can_create_pseudo_p ()) - { - emit_move_insn (dest_hi, tmp_hi); - emit_move_insn (dest_lo, tmp_lo); - } - DONE; -} - [(set_attr "length" "8") - (set_attr "type" "mul") - (set_attr "size" "64")]) - -(define_insn "<u>mulditi3_<u>adddi3_upper" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (truncate:DI - (lshiftrt:TI - (plus:TI - (mult:TI - (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r")) - (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r"))) - (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r"))) - (const_int 64))))] - "TARGET_MADDLD && TARGET_POWERPC64" - "maddhd<u> %0,%1,%2,%3" - [(set_attr "type" "mul") - (set_attr "size" "64")]) - (define_insn "udiv<mode>3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
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