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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work087)] Update ChangeLog.meissner.
Date: Mon,  2 May 2022 21:14:18 +0000 (GMT)	[thread overview]
Message-ID: <20220502211418.62BBD3858C51@sourceware.org> (raw)

https://gcc.gnu.org/g:2c8e183c040c5b87155adeb2744c7c0a0b3a4a08

commit 2c8e183c040c5b87155adeb2744c7c0a0b3a4a08
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Mon May 2 17:13:55 2022 -0400

    Update ChangeLog.meissner.
    
    2022-05-02   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 10ec93d7c81..0368d51da3d 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,16 @@
+==================== work087, patch #9:
+
+Add support for power10 128-bit shifts.
+
+2022-05-02   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+	* config/rs6000/altivec.md (ti_shift): New code iterator.
+	(ti_shift_insn): New code attribute.
+	(ti_shift_name): New code attribute.
+	(<ti_shift_name><mode>3): Add support for 128-bit integer shift
+	right, left, and arithmetic right using power10 instructions.
+
 ==================== work087, patch #8:
 
 Generate vadduqm and vsubuqm for TImode add/subtract


             reply	other threads:[~2022-05-02 21:14 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-02 21:14 Michael Meissner [this message]
  -- strict thread matches above, loose matches on Subject: below --
2022-04-28 21:15 Michael Meissner
2022-04-27 15:46 Michael Meissner
2022-04-27 15:45 Michael Meissner
2022-04-27 15:41 Michael Meissner

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