From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2049) id DB4353856DF5; Thu, 5 May 2022 12:04:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DB4353856DF5 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Matthew Malcomson To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/morello)] aarch64: Add pointer_plus base+index patterns X-Act-Checkin: gcc X-Git-Author: Richard Sandiford X-Git-Refname: refs/vendors/ARM/heads/morello X-Git-Oldrev: 7b533cd785ed59adb3bdd5d49a0b3fcb43624301 X-Git-Newrev: 38dadd6639ea3fafe9b92fd40dba2cff3ec90844 Message-Id: <20220505120454.DB4353856DF5@sourceware.org> Date: Thu, 5 May 2022 12:04:54 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 May 2022 12:04:55 -0000 https://gcc.gnu.org/g:38dadd6639ea3fafe9b92fd40dba2cff3ec90844 commit 38dadd6639ea3fafe9b92fd40dba2cff3ec90844 Author: Richard Sandiford Date: Fri Mar 18 15:23:35 2022 +0000 aarch64: Add pointer_plus base+index patterns This patch adds pointer_plus versions of the GPI base+index address patterns, using shift to represent scaling. This includes fixing aarch64_uxt_size to allow the full UXT range: [0, 4]. Diff: --- gcc/config/aarch64/aarch64-morello.md | 52 ++++ gcc/config/aarch64/aarch64.c | 2 +- .../gcc.target/aarch64/morello/pointer-arith-1.c | 266 +++++++++++++++++++++ .../gcc.target/aarch64/morello/pointer-arith-1.h | 9 + .../gcc.target/aarch64/morello/pointer-arith-2.c | 266 +++++++++++++++++++++ 5 files changed, 594 insertions(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64-morello.md b/gcc/config/aarch64/aarch64-morello.md index 7ddba8b15f6..d1ed7c03055 100644 --- a/gcc/config/aarch64/aarch64-morello.md +++ b/gcc/config/aarch64/aarch64-morello.md @@ -30,6 +30,58 @@ sub\\t%0, %1, #%n2" ) +(define_insn "*pointer_plus_lsl_cadi" + [(set (match_operand:CADI 0 "register_operand" "=r") + (pointer_plus:CADI + (match_operand:CADI 1 "register_operand" "r") + (ashift:DI (match_operand:DI 2 "register_operand" "r") + (match_operand:QI 3 "aarch64_imm3"))))] + "TARGET_CAPABILITY_ANY" + "add\\t%0, %1, %2, lsl %3" + [(set_attr "type" "alu_shift_imm")] +) + +(define_insn "*pointer_plus__cadi" + [(set (match_operand:CADI 0 "register_operand" "=rk") + (pointer_plus:CADI + (match_operand:CADI 1 "register_operand" "r") + (ANY_EXTEND:DI (match_operand:ALLX 2 "register_operand" "r"))))] + "TARGET_CAPABILITY_ANY" + "add\t%0, %1, %w2, xt" + [(set_attr "type" "alu_ext")] +) + +(define_insn "*pointer_plus__lsl_cadi" + [(set (match_operand:CADI 0 "register_operand" "=rk") + (pointer_plus:CADI + (match_operand:CADI 1 "register_operand" "r") + (ashift:DI + (ANY_EXTEND:DI + (match_operand:ALLX 2 "register_operand" "r")) + (match_operand 3 "aarch64_imm3"))))] + "TARGET_CAPABILITY_ANY" + "add\t%0, %1, %w2, xt %3" + [(set_attr "type" "alu_ext")] +) + +(define_insn "*pointer_plus_and_lsl_cadi" + [(set (match_operand:CADI 0 "register_operand" "=rk") + (pointer_plus:CADI + (match_operand:CADI 1 "register_operand" "r") + (and:DI + (ashift:DI (match_operand:DI 2 "register_operand" "r") + (match_operand 3 "aarch64_imm3")) + (match_operand:DI 4 "const_int_operand"))))] + "TARGET_CAPABILITY_ANY + && aarch64_uxt_size (INTVAL (operands[3]), INTVAL (operands[4])) != 0" + { + operands[4] = GEN_INT (aarch64_uxt_size (INTVAL (operands[3]), + INTVAL (operands[4]))); + return "add\t%0, %1, %w2, uxt%e4 %3"; + } + [(set_attr "type" "alu_ext")] +) + ; TODO: many more alternatives. (define_insn "*movcadi_aarch64" [(set (match_operand:CADI 0 "nonimmediate_operand" "=rk,r,r,m,r,r") diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 94863bb8188..0cc5467a29a 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -11882,7 +11882,7 @@ aarch64_output_casesi (rtx *operands) int aarch64_uxt_size (int shift, HOST_WIDE_INT mask) { - if (shift >= 0 && shift <= 3) + if (shift >= 0 && shift <= 4) { int size; for (size = 8; size <= 32; size *= 2) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/pointer-arith-1.c b/gcc/testsuite/gcc.target/aarch64/morello/pointer-arith-1.c new file mode 100644 index 00000000000..117d5010d64 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/pointer-arith-1.c @@ -0,0 +1,266 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-std=gnu11 -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ +/* { dg-skip-if "" { *-*-* } { "-mfake-capability" } { "" } } */ + +#include "pointer-arith-1.h" + +/* +** test_int8_t_1: +** add c0, c0, w1, sxtb +** ret +*/ +TEST (int8_t, 1) + +/* +** test_uint8_t_1: +** add c0, c0, w1, uxtb +** ret +*/ +TEST (uint8_t, 1) + +/* +** test_int8_t_2: +** add c0, c0, w1, sxtb #?1 +** ret +*/ +TEST (int8_t, 2) + +/* +** test_uint8_t_2: +** add c0, c0, w1, uxtb #?1 +** ret +*/ +TEST (uint8_t, 2) + +/* +** test_int8_t_4: +** add c0, c0, w1, sxtb #?2 +** ret +*/ +TEST (int8_t, 4) + +/* +** test_uint8_t_4: +** add c0, c0, w1, uxtb #?2 +** ret +*/ +TEST (uint8_t, 4) + +/* +** test_int8_t_8: +** add c0, c0, w1, sxtb #?3 +** ret +*/ +TEST (int8_t, 8) + +/* +** test_uint8_t_8: +** add c0, c0, w1, uxtb #?3 +** ret +*/ +TEST (uint8_t, 8) + +/* +** test_int8_t_16: +** add c0, c0, w1, sxtb #?4 +** ret +*/ +TEST (int8_t, 16) + +/* +** test_uint8_t_16: +** add c0, c0, w1, uxtb #?4 +** ret +*/ +TEST (uint8_t, 16) + +/* Check for valid asm, but don't mandate a particular sequence. */ +TEST (int8_t, 32) +TEST (uint8_t, 32) + +/* +** test_int16_t_1: +** add c0, c0, w1, sxth +** ret +*/ +TEST (int16_t, 1) + +/* +** test_uint16_t_1: +** add c0, c0, w1, uxth +** ret +*/ +TEST (uint16_t, 1) + +/* +** test_int16_t_2: +** add c0, c0, w1, sxth #?1 +** ret +*/ +TEST (int16_t, 2) + +/* +** test_uint16_t_2: +** add c0, c0, w1, uxth #?1 +** ret +*/ +TEST (uint16_t, 2) + +/* +** test_int16_t_4: +** add c0, c0, w1, sxth #?2 +** ret +*/ +TEST (int16_t, 4) + +/* +** test_uint16_t_4: +** add c0, c0, w1, uxth #?2 +** ret +*/ +TEST (uint16_t, 4) + +/* +** test_int16_t_8: +** add c0, c0, w1, sxth #?3 +** ret +*/ +TEST (int16_t, 8) + +/* +** test_uint16_t_8: +** add c0, c0, w1, uxth #?3 +** ret +*/ +TEST (uint16_t, 8) + +/* +** test_int16_t_16: +** add c0, c0, w1, sxth #?4 +** ret +*/ +TEST (int16_t, 16) + +/* +** test_uint16_t_16: +** add c0, c0, w1, uxth #?4 +** ret +*/ +TEST (uint16_t, 16) + +/* Check for valid asm, but don't mandate a particular sequence. */ +TEST (int16_t, 32) +TEST (uint16_t, 32) + +/* +** test_int32_t_1: +** add c0, c0, w1, sxtw +** ret +*/ +TEST (int32_t, 1) + +/* +** test_uint32_t_1: +** add c0, c0, w1, uxtw +** ret +*/ +TEST (uint32_t, 1) + +/* +** test_int32_t_2: +** add c0, c0, w1, sxtw #?1 +** ret +*/ +TEST (int32_t, 2) + +/* +** test_uint32_t_2: +** add c0, c0, w1, uxtw #?1 +** ret +*/ +TEST (uint32_t, 2) + +/* +** test_int32_t_4: +** add c0, c0, w1, sxtw #?2 +** ret +*/ +TEST (int32_t, 4) + +/* +** test_uint32_t_4: +** add c0, c0, w1, uxtw #?2 +** ret +*/ +TEST (uint32_t, 4) + +/* +** test_int32_t_8: +** add c0, c0, w1, sxtw #?3 +** ret +*/ +TEST (int32_t, 8) + +/* +** test_uint32_t_8: +** add c0, c0, w1, uxtw #?3 +** ret +*/ +TEST (uint32_t, 8) + +/* +** test_int32_t_16: +** add c0, c0, w1, sxtw #?4 +** ret +*/ +TEST (int32_t, 16) + +/* +** test_uint32_t_16: +** add c0, c0, w1, uxtw #?4 +** ret +*/ +TEST (uint32_t, 16) + +/* Check for valid asm, but don't mandate a particular sequence. */ +TEST (int32_t, 32) +TEST (uint32_t, 32) + +/* +** test_uint64_t_1: +** add c0, c0, x1 +** ret +*/ +TEST (uint64_t, 1) + +/* +** test_uint64_t_2: +** add c0, c0, x1, lsl #?1 +** ret +*/ +TEST (uint64_t, 2) + +/* +** test_uint64_t_4: +** add c0, c0, x1, lsl #?2 +** ret +*/ +TEST (uint64_t, 4) + +/* +** test_uint64_t_8: +** add c0, c0, x1, lsl #?3 +** ret +*/ +TEST (uint64_t, 8) + +/* +** test_uint64_t_16: +** add c0, c0, x1, lsl #?4 +** ret +*/ +TEST (uint64_t, 16) + +/* Check for valid asm, but don't mandate a particular sequence. */ +TEST (uint64_t, 32) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/pointer-arith-1.h b/gcc/testsuite/gcc.target/aarch64/morello/pointer-arith-1.h new file mode 100644 index 00000000000..aea25b3dfad --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/pointer-arith-1.h @@ -0,0 +1,9 @@ +#include +#include + +#define TEST(TYPE, SCALE) \ + char *__capability \ + test_##TYPE##_##SCALE (char *__capability base, TYPE index) \ + { \ + return base + (ptrdiff_t) index * SCALE; \ + } diff --git a/gcc/testsuite/gcc.target/aarch64/morello/pointer-arith-2.c b/gcc/testsuite/gcc.target/aarch64/morello/pointer-arith-2.c new file mode 100644 index 00000000000..480b7267d02 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/pointer-arith-2.c @@ -0,0 +1,266 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-std=gnu11 -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ +/* { dg-skip-if "" { *-*-* } { "*" } { "-mfake-capability" } } */ + +#include "pointer-arith-1.h" + +/* +** test_int8_t_1: +** add x0, x0, w1, sxtb +** ret +*/ +TEST (int8_t, 1) + +/* +** test_uint8_t_1: +** add x0, x0, w1, uxtb +** ret +*/ +TEST (uint8_t, 1) + +/* +** test_int8_t_2: +** add x0, x0, w1, sxtb #?1 +** ret +*/ +TEST (int8_t, 2) + +/* +** test_uint8_t_2: +** add x0, x0, w1, uxtb #?1 +** ret +*/ +TEST (uint8_t, 2) + +/* +** test_int8_t_4: +** add x0, x0, w1, sxtb #?2 +** ret +*/ +TEST (int8_t, 4) + +/* +** test_uint8_t_4: +** add x0, x0, w1, uxtb #?2 +** ret +*/ +TEST (uint8_t, 4) + +/* +** test_int8_t_8: +** add x0, x0, w1, sxtb #?3 +** ret +*/ +TEST (int8_t, 8) + +/* +** test_uint8_t_8: +** add x0, x0, w1, uxtb #?3 +** ret +*/ +TEST (uint8_t, 8) + +/* +** test_int8_t_16: +** add x0, x0, w1, sxtb #?4 +** ret +*/ +TEST (int8_t, 16) + +/* +** test_uint8_t_16: +** add x0, x0, w1, uxtb #?4 +** ret +*/ +TEST (uint8_t, 16) + +/* Check for valid asm, but don't mandate a particular sequence. */ +TEST (int8_t, 32) +TEST (uint8_t, 32) + +/* +** test_int16_t_1: +** add x0, x0, w1, sxth +** ret +*/ +TEST (int16_t, 1) + +/* +** test_uint16_t_1: +** add x0, x0, w1, uxth +** ret +*/ +TEST (uint16_t, 1) + +/* +** test_int16_t_2: +** add x0, x0, w1, sxth #?1 +** ret +*/ +TEST (int16_t, 2) + +/* +** test_uint16_t_2: +** add x0, x0, w1, uxth #?1 +** ret +*/ +TEST (uint16_t, 2) + +/* +** test_int16_t_4: +** add x0, x0, w1, sxth #?2 +** ret +*/ +TEST (int16_t, 4) + +/* +** test_uint16_t_4: +** add x0, x0, w1, uxth #?2 +** ret +*/ +TEST (uint16_t, 4) + +/* +** test_int16_t_8: +** add x0, x0, w1, sxth #?3 +** ret +*/ +TEST (int16_t, 8) + +/* +** test_uint16_t_8: +** add x0, x0, w1, uxth #?3 +** ret +*/ +TEST (uint16_t, 8) + +/* +** test_int16_t_16: +** add x0, x0, w1, sxth #?4 +** ret +*/ +TEST (int16_t, 16) + +/* +** test_uint16_t_16: +** add x0, x0, w1, uxth #?4 +** ret +*/ +TEST (uint16_t, 16) + +/* Check for valid asm, but don't mandate a particular sequence. */ +TEST (int16_t, 32) +TEST (uint16_t, 32) + +/* +** test_int32_t_1: +** add x0, x0, w1, sxtw +** ret +*/ +TEST (int32_t, 1) + +/* +** test_uint32_t_1: +** add x0, x0, w1, uxtw +** ret +*/ +TEST (uint32_t, 1) + +/* +** test_int32_t_2: +** add x0, x0, w1, sxtw #?1 +** ret +*/ +TEST (int32_t, 2) + +/* +** test_uint32_t_2: +** add x0, x0, w1, uxtw #?1 +** ret +*/ +TEST (uint32_t, 2) + +/* +** test_int32_t_4: +** add x0, x0, w1, sxtw #?2 +** ret +*/ +TEST (int32_t, 4) + +/* +** test_uint32_t_4: +** add x0, x0, w1, uxtw #?2 +** ret +*/ +TEST (uint32_t, 4) + +/* +** test_int32_t_8: +** add x0, x0, w1, sxtw #?3 +** ret +*/ +TEST (int32_t, 8) + +/* +** test_uint32_t_8: +** add x0, x0, w1, uxtw #?3 +** ret +*/ +TEST (uint32_t, 8) + +/* +** test_int32_t_16: +** add x0, x0, w1, sxtw #?4 +** ret +*/ +TEST (int32_t, 16) + +/* +** test_uint32_t_16: +** add x0, x0, w1, uxtw #?4 +** ret +*/ +TEST (uint32_t, 16) + +/* Check for valid asm, but don't mandate a particular sequence. */ +TEST (int32_t, 32) +TEST (uint32_t, 32) + +/* +** test_uint64_t_1: +** add x0, x0, x1 +** ret +*/ +TEST (uint64_t, 1) + +/* +** test_uint64_t_2: +** add x0, x0, x1, lsl #?1 +** ret +*/ +TEST (uint64_t, 2) + +/* +** test_uint64_t_4: +** add x0, x0, x1, lsl #?2 +** ret +*/ +TEST (uint64_t, 4) + +/* +** test_uint64_t_8: +** add x0, x0, x1, lsl #?3 +** ret +*/ +TEST (uint64_t, 8) + +/* +** test_uint64_t_16: +** add x0, x0, x1, lsl #?4 +** ret +*/ +TEST (uint64_t, 16) + +/* Check for valid asm, but don't mandate a particular sequence. */ +TEST (uint64_t, 32)