From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2049) id 648953856262; Thu, 5 May 2022 12:05:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 648953856262 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Matthew Malcomson To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/morello)] aarch64: Some movcadi-related fixes X-Act-Checkin: gcc X-Git-Author: Richard Sandiford X-Git-Refname: refs/vendors/ARM/heads/morello X-Git-Oldrev: b2686ea200f80dce1b900ab782e99a81f030331e X-Git-Newrev: ed21bbaca004b342e38970738d1b574d492df4fb Message-Id: <20220505120530.648953856262@sourceware.org> Date: Thu, 5 May 2022 12:05:30 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 May 2022 12:05:30 -0000 https://gcc.gnu.org/g:ed21bbaca004b342e38970738d1b574d492df4fb commit ed21bbaca004b342e38970738d1b574d492df4fb Author: Richard Sandiford Date: Thu Apr 7 13:25:22 2022 +0100 aarch64: Some movcadi-related fixes - Allow indexed addressing for LDR/STR Cn - Allow CZR to be saved directly - Enable CADI moves for hybrid (normal base only for now) Diff: --- gcc/config/aarch64/aarch64-morello.md | 8 +- gcc/config/aarch64/aarch64.c | 6 + .../gcc.target/aarch64/morello/load-store-utils.h | 82 ++++++++++ .../aarch64/morello/normal-base-load-cadi-1.c | 173 +++++++++++++++++++++ .../aarch64/morello/normal-base-store-cadi-1.c | 173 +++++++++++++++++++++ .../aarch64/morello/normal-base-store-cadi-2.c | 173 +++++++++++++++++++++ 6 files changed, 611 insertions(+), 4 deletions(-) diff --git a/gcc/config/aarch64/aarch64-morello.md b/gcc/config/aarch64/aarch64-morello.md index d1ed7c03055..7cddee9c075 100644 --- a/gcc/config/aarch64/aarch64-morello.md +++ b/gcc/config/aarch64/aarch64-morello.md @@ -107,14 +107,14 @@ }) (define_insn "*movcadi_aarch64" - [(set (match_operand:CADI 0 "nonimmediate_operand" "=rk,r,r,m,r ,r ") - (match_operand:CADI 1 "aarch64_mov_operand" "rk ,Z,m,r,Usa,Ush"))] - "TARGET_CAPABILITY_PURE" + [(set (match_operand:CADI 0 "nonimmediate_operand" "=rk,r,r,m, r ,r ") + (match_operand:CADI 1 "aarch64_mov_operand" "rk ,Z,m,rZ,Usa,Ush"))] + "TARGET_MORELLO" "@ mov\\t%0, %1 mov\\t%x0, xzr ldr\\t%0, %1 - str\\t%1, %0 + str\\t%B1, %0 adr\\t%0, %c1 adrp\\t%0, %A1" ) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ae6ff9abc9d..cb7e4b7ff74 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -9580,6 +9580,11 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x, || (1 << shift) != GET_MODE_UNIT_SIZE (mode)) return false; } + else if (TARGET_MORELLO && mode == CADImode) + { + if (shift != 0 && shift != 4) + return false; + } else { if (shift != 0 @@ -9667,6 +9672,7 @@ aarch64_classify_address (struct aarch64_address_info *info, bool allow_reg_index_p = (!load_store_pair_p && (known_lt (GET_MODE_SIZE (mode), 16) + || mode == CADImode || vec_flags == VEC_ADVSIMD || vec_flags & VEC_SVE_DATA)); diff --git a/gcc/testsuite/gcc.target/aarch64/morello/load-store-utils.h b/gcc/testsuite/gcc.target/aarch64/morello/load-store-utils.h new file mode 100644 index 00000000000..f15197a4c1f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/load-store-utils.h @@ -0,0 +1,82 @@ +#include +#include + +#define m272 -272 +#define m257 -257 +#define m256 -256 +#define m255 -255 +#define m240 -240 +#define m16 -16 +#define m1 -1 + +#define LOAD_REG_OFFSET(REG, TYPE, OFFSET) \ + void \ + load_##REG##_##TYPE##_##OFFSET (char *base) \ + { \ + register TYPE reg asm (#REG); \ + TYPE *ptr = (TYPE *) (base + OFFSET); \ + asm volatile ("" : "=rw" (reg) : "0" (*ptr)); \ + } + +#define LOAD_REG_INDEX(REG, TYPE, INDEX_TYPE, SCALE) \ + void \ + load_##REG##_##TYPE##_##INDEX_TYPE##_##SCALE (char *base, \ + INDEX_TYPE index) \ + { \ + register TYPE reg asm (#REG); \ + ptrdiff_t byte_index = (ptrdiff_t) index * SCALE; \ + TYPE *ptr = (TYPE *) (base + byte_index); \ + asm volatile ("" : "=rw" (reg) : "0" (*ptr)); \ + } + +#define STORE_REG_OFFSET(REG, TYPE, OFFSET) \ + void \ + store_##REG##_##TYPE##_##OFFSET (char *base) \ + { \ + register TYPE reg asm (#REG); \ + TYPE *ptr = (TYPE *) (base + OFFSET); \ + asm ("" : "=rw" (reg)); \ + *ptr = reg; \ + } + +#define STORE_REG_INDEX(REG, TYPE, INDEX_TYPE, SCALE) \ + void \ + store_##REG##_##TYPE##_##INDEX_TYPE##_##SCALE (char *base, \ + INDEX_TYPE index) \ + { \ + register TYPE reg asm (#REG); \ + ptrdiff_t byte_index = (ptrdiff_t) index * SCALE; \ + TYPE *ptr = (TYPE *) (base + byte_index); \ + asm ("" : "=rw" (reg)); \ + *ptr = reg; \ + } + +#define STORE_ZERO_OFFSET(TYPE, OFFSET) \ + void \ + store_zero_##TYPE##_##OFFSET (char *base) \ + { \ + TYPE *ptr = (TYPE *) (base + OFFSET); \ + *ptr = 0; \ + } + +#define STORE_REG_INDEX(REG, TYPE, INDEX_TYPE, SCALE) \ + void \ + store_##REG##_##TYPE##_##INDEX_TYPE##_##SCALE (char *base, \ + INDEX_TYPE index) \ + { \ + register TYPE reg asm (#REG); \ + ptrdiff_t byte_index = (ptrdiff_t) index * SCALE; \ + TYPE *ptr = (TYPE *) (base + byte_index); \ + asm ("" : "=rw" (reg)); \ + *ptr = reg; \ + } + +#define STORE_ZERO_INDEX(TYPE, INDEX_TYPE, SCALE) \ + void \ + store_zero_##TYPE##_##INDEX_TYPE##_##SCALE (char *base, \ + INDEX_TYPE index) \ + { \ + ptrdiff_t byte_index = (ptrdiff_t) index * SCALE; \ + TYPE *ptr = (TYPE *) (base + byte_index); \ + *ptr = 0; \ + } diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-load-cadi-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-load-cadi-1.c new file mode 100644 index 00000000000..b0e6951af1a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-load-cadi-1.c @@ -0,0 +1,173 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ +/* { dg-skip-if "" { *-*-* } { "-mfake-capability" } { "" } } */ + +#include "load-store-utils.h" + +typedef __uintcap_t uintcap_t; + +/* +** load_c10_uintcap_t_m272: +** ( +** sub (c[0-9]+), c0, #272 +** ldr c10, \[\1\] +** | +** sub (x[0-9]+), x0, #65536 +** ldr c10, \[\2, #?65264\] +** ) +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, m272) + +/* +** load_c10_uintcap_t_m257: +** ( +** sub (c[0-9]+), c0, #257 +** ldr c10, \[\1\] +** | +** sub (x[0-9]+), x0, #512 +** ldr c10, \[\2, #?255\] +** ) +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, m257) + +/* +** load_c10_uintcap_t_m256: +** ldr c10, \[[cx]0, #?-256\] +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, m256) + +/* +** load_c10_uintcap_t_m255: +** ldr c10, \[[cx]0, #?-255\] +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, m255) + +/* +** load_c10_uintcap_t_m16: +** ldr c10, \[[cx]0, #?-16\] +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, m16) + +/* +** load_c10_uintcap_t_m1: +** ldr c10, \[[cx]0, #?-1\] +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, m1) + +/* +** load_c10_uintcap_t_1: +** ldr c10, \[[cx]0, #?1\] +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, 1) + +/* +** load_c10_uintcap_t_16: +** ldr c10, \[[cx]0, #?16\] +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, 16) + +/* +** load_c10_uintcap_t_255: +** ldr c10, \[[cx]0, #?255\] +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, 255) + +/* +** load_c10_uintcap_t_256: +** ldr c10, \[[cx]0, #?256\] +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, 256) + +/* +** load_c10_uintcap_t_257: +** ( +** add (c[0-9]+), c0, #?256 +** ldr c10, \[\1, #?1\] +** | +** add (x[0-9]+), x0, #?512 +** ldr c10, \[\2, #?-255\] +** ) +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, 257) + +/* +** load_c10_uintcap_t_65520: +** ldr c10, \[[cx]0, #?65520\] +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, 65520) + +/* +** load_c10_uintcap_t_65536: +** add ([xc][0-9]+), [cx]0, #?65536 +** ldr c10, \[\1\] +** ret +*/ +LOAD_REG_OFFSET (c10, uintcap_t, 65536) + +/* +** load_c10_uintcap_t_int32_t_1: +** ldr c10, \[[cx]0, w1, sxtw\] +** ret +*/ +LOAD_REG_INDEX (c10, uintcap_t, int32_t, 1) + +/* +** load_c10_uintcap_t_uint32_t_1: +** ldr c10, \[[cx]0, w1, uxtw\] +** ret +*/ +LOAD_REG_INDEX (c10, uintcap_t, uint32_t, 1) + +/* +** load_c10_uintcap_t_uint64_t_1: +** ldr c10, \[[cx]0, x1\] +** ret +*/ +LOAD_REG_INDEX (c10, uintcap_t, uint64_t, 1) + +/* Check for valid asm, but don't mandate a particular sequence. */ +LOAD_REG_INDEX (c10, uintcap_t, int32_t, 2) +LOAD_REG_INDEX (c10, uintcap_t, uint32_t, 2) +LOAD_REG_INDEX (c10, uintcap_t, uint64_t, 2) + +LOAD_REG_INDEX (c10, uintcap_t, int32_t, 4) +LOAD_REG_INDEX (c10, uintcap_t, uint32_t, 4) +LOAD_REG_INDEX (c10, uintcap_t, uint64_t, 4) + +LOAD_REG_INDEX (c10, uintcap_t, int32_t, 8) +LOAD_REG_INDEX (c10, uintcap_t, uint32_t, 8) +LOAD_REG_INDEX (c10, uintcap_t, uint64_t, 8) + +/* +** load_c10_uintcap_t_int32_t_16: +** ldr c10, \[[cx]0, w1, sxtw #?4\] +** ret +*/ +LOAD_REG_INDEX (c10, uintcap_t, int32_t, 16) + +/* +** load_c10_uintcap_t_uint32_t_16: +** ldr c10, \[[cx]0, w1, uxtw #?4\] +** ret +*/ +LOAD_REG_INDEX (c10, uintcap_t, uint32_t, 16) + +/* +** load_c10_uintcap_t_uint64_t_16: +** ldr c10, \[[cx]0, x1, lsl #?4\] +** ret +*/ +LOAD_REG_INDEX (c10, uintcap_t, uint64_t, 16) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-store-cadi-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-store-cadi-1.c new file mode 100644 index 00000000000..7159161b1ed --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-store-cadi-1.c @@ -0,0 +1,173 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ +/* { dg-skip-if "" { *-*-* } { "-mfake-capability" } { "" } } */ + +#include "load-store-utils.h" + +typedef __uintcap_t uintcap_t; + +/* +** store_c10_uintcap_t_m272: +** ( +** sub (c[0-9]+), c0, #272 +** str c10, \[\1\] +** | +** sub (x[0-9]+), x0, #65536 +** str c10, \[\2, #?65264\] +** ) +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, m272) + +/* +** store_c10_uintcap_t_m257: +** ( +** sub (c[0-9]+), c0, #257 +** str c10, \[\1\] +** | +** sub (x[0-9]+), x0, #512 +** str c10, \[\2, #?255\] +** ) +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, m257) + +/* +** store_c10_uintcap_t_m256: +** str c10, \[[xc]0, #?-256\] +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, m256) + +/* +** store_c10_uintcap_t_m255: +** str c10, \[[xc]0, #?-255\] +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, m255) + +/* +** store_c10_uintcap_t_m16: +** str c10, \[[xc]0, #?-16\] +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, m16) + +/* +** store_c10_uintcap_t_m1: +** str c10, \[[xc]0, #?-1\] +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, m1) + +/* +** store_c10_uintcap_t_1: +** str c10, \[[xc]0, #?1\] +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, 1) + +/* +** store_c10_uintcap_t_16: +** str c10, \[[xc]0, #?16\] +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, 16) + +/* +** store_c10_uintcap_t_255: +** str c10, \[[xc]0, #?255\] +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, 255) + +/* +** store_c10_uintcap_t_256: +** str c10, \[[xc]0, #?256\] +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, 256) + +/* +** store_c10_uintcap_t_257: +** ( +** add (c[0-9]+), c0, #?256 +** str c10, \[\1, #?1\] +** | +** add (x[0-9]+), x0, #?512 +** str c10, \[\2, #?-255\] +** ) +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, 257) + +/* +** store_c10_uintcap_t_65520: +** str c10, \[[xc]0, #?65520\] +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, 65520) + +/* +** store_c10_uintcap_t_65536: +** add ([xc][0-9]+), [xc]0, #?65536 +** str c10, \[\1\] +** ret +*/ +STORE_REG_OFFSET (c10, uintcap_t, 65536) + +/* +** store_c10_uintcap_t_int32_t_1: +** str c10, \[[xc]0, w1, sxtw\] +** ret +*/ +STORE_REG_INDEX (c10, uintcap_t, int32_t, 1) + +/* +** store_c10_uintcap_t_uint32_t_1: +** str c10, \[[xc]0, w1, uxtw\] +** ret +*/ +STORE_REG_INDEX (c10, uintcap_t, uint32_t, 1) + +/* +** store_c10_uintcap_t_uint64_t_1: +** str c10, \[[xc]0, x1\] +** ret +*/ +STORE_REG_INDEX (c10, uintcap_t, uint64_t, 1) + +/* Check for valid asm, but don't mandate a particular sequence. */ +STORE_REG_INDEX (c10, uintcap_t, int32_t, 2) +STORE_REG_INDEX (c10, uintcap_t, uint32_t, 2) +STORE_REG_INDEX (c10, uintcap_t, uint64_t, 2) + +STORE_REG_INDEX (c10, uintcap_t, int32_t, 4) +STORE_REG_INDEX (c10, uintcap_t, uint32_t, 4) +STORE_REG_INDEX (c10, uintcap_t, uint64_t, 4) + +STORE_REG_INDEX (c10, uintcap_t, int32_t, 8) +STORE_REG_INDEX (c10, uintcap_t, uint32_t, 8) +STORE_REG_INDEX (c10, uintcap_t, uint64_t, 8) + +/* +** store_c10_uintcap_t_int32_t_16: +** str c10, \[[xc]0, w1, sxtw #?4\] +** ret +*/ +STORE_REG_INDEX (c10, uintcap_t, int32_t, 16) + +/* +** store_c10_uintcap_t_uint32_t_16: +** str c10, \[[xc]0, w1, uxtw #?4\] +** ret +*/ +STORE_REG_INDEX (c10, uintcap_t, uint32_t, 16) + +/* +** store_c10_uintcap_t_uint64_t_16: +** str c10, \[[xc]0, x1, lsl #?4\] +** ret +*/ +STORE_REG_INDEX (c10, uintcap_t, uint64_t, 16) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-store-cadi-2.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-store-cadi-2.c new file mode 100644 index 00000000000..0860142b027 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-store-cadi-2.c @@ -0,0 +1,173 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ +/* { dg-skip-if "" { *-*-* } { "-mfake-capability" } { "" } } */ + +#include "load-store-utils.h" + +typedef __uintcap_t uintcap_t; + +/* +** store_zero_uintcap_t_m272: +** ( +** sub (c[0-9]+), c0, #272 +** str czr, \[\1\] +** | +** sub (x[0-9]+), x0, #65536 +** str czr, \[\2, #?65264\] +** ) +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, m272) + +/* +** store_zero_uintcap_t_m257: +** ( +** sub (c[0-9]+), c0, #257 +** str czr, \[\1\] +** | +** sub (x[0-9]+), x0, #512 +** str czr, \[\2, #?255\] +** ) +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, m257) + +/* +** store_zero_uintcap_t_m256: +** str czr, \[[xc]0, #?-256\] +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, m256) + +/* +** store_zero_uintcap_t_m255: +** str czr, \[[xc]0, #?-255\] +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, m255) + +/* +** store_zero_uintcap_t_m16: +** str czr, \[[xc]0, #?-16\] +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, m16) + +/* +** store_zero_uintcap_t_m1: +** str czr, \[[xc]0, #?-1\] +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, m1) + +/* +** store_zero_uintcap_t_1: +** str czr, \[[xc]0, #?1\] +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, 1) + +/* +** store_zero_uintcap_t_16: +** str czr, \[[xc]0, #?16\] +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, 16) + +/* +** store_zero_uintcap_t_255: +** str czr, \[[xc]0, #?255\] +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, 255) + +/* +** store_zero_uintcap_t_256: +** str czr, \[[xc]0, #?256\] +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, 256) + +/* +** store_zero_uintcap_t_257: +** ( +** add (c[0-9]+), c0, #?256 +** str czr, \[\1, #?1\] +** | +** add (x[0-9]+), x0, #?512 +** str czr, \[\2, #?-255\] +** ) +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, 257) + +/* +** store_zero_uintcap_t_65520: +** str czr, \[[xc]0, #?65520\] +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, 65520) + +/* +** store_zero_uintcap_t_65536: +** add ([xc][0-9]+), [xc]0, #?65536 +** str czr, \[\1\] +** ret +*/ +STORE_ZERO_OFFSET (uintcap_t, 65536) + +/* +** store_zero_uintcap_t_int32_t_1: +** str czr, \[[xc]0, w1, sxtw\] +** ret +*/ +STORE_ZERO_INDEX (uintcap_t, int32_t, 1) + +/* +** store_zero_uintcap_t_uint32_t_1: +** str czr, \[[xc]0, w1, uxtw\] +** ret +*/ +STORE_ZERO_INDEX (uintcap_t, uint32_t, 1) + +/* +** store_zero_uintcap_t_uint64_t_1: +** str czr, \[[xc]0, x1\] +** ret +*/ +STORE_ZERO_INDEX (uintcap_t, uint64_t, 1) + +/* Check for valid asm, but don't mandate a particular sequence. */ +STORE_ZERO_INDEX (uintcap_t, int32_t, 2) +STORE_ZERO_INDEX (uintcap_t, uint32_t, 2) +STORE_ZERO_INDEX (uintcap_t, uint64_t, 2) + +STORE_ZERO_INDEX (uintcap_t, int32_t, 4) +STORE_ZERO_INDEX (uintcap_t, uint32_t, 4) +STORE_ZERO_INDEX (uintcap_t, uint64_t, 4) + +STORE_ZERO_INDEX (uintcap_t, int32_t, 8) +STORE_ZERO_INDEX (uintcap_t, uint32_t, 8) +STORE_ZERO_INDEX (uintcap_t, uint64_t, 8) + +/* +** store_zero_uintcap_t_int32_t_16: +** str czr, \[[xc]0, w1, sxtw #?4\] +** ret +*/ +STORE_ZERO_INDEX (uintcap_t, int32_t, 16) + +/* +** store_zero_uintcap_t_uint32_t_16: +** str czr, \[[xc]0, w1, uxtw #?4\] +** ret +*/ +STORE_ZERO_INDEX (uintcap_t, uint32_t, 16) + +/* +** store_zero_uintcap_t_uint64_t_16: +** str czr, \[[xc]0, x1, lsl #?4\] +** ret +*/ +STORE_ZERO_INDEX (uintcap_t, uint64_t, 16)