From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2049) id 6D92D385DC20; Thu, 5 May 2022 12:06:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6D92D385DC20 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Matthew Malcomson To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/morello)] Various auto-inc fixes for capabilities X-Act-Checkin: gcc X-Git-Author: Richard Sandiford X-Git-Refname: refs/vendors/ARM/heads/morello X-Git-Oldrev: 98a1d8bef1c8ffe320d2eda5b4cdd8de15786b28 X-Git-Newrev: 7d455a032ba1fbd1efc991b576d5bd8329f736e2 Message-Id: <20220505120641.6D92D385DC20@sourceware.org> Date: Thu, 5 May 2022 12:06:41 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 May 2022 12:06:41 -0000 https://gcc.gnu.org/g:7d455a032ba1fbd1efc991b576d5bd8329f736e2 commit 7d455a032ba1fbd1efc991b576d5bd8329f736e2 Author: Richard Sandiford Date: Thu Mar 31 17:09:31 2022 +0100 Various auto-inc fixes for capabilities This patch makes auto-inc-dec.c handle capability address calculations, so that purecap code can use pre-modify and post-modify forms with Cn addresses. However, there are no alternative-base pre-modify or post-modify forms for any access size, so we should completely disable them for Cn addresses on hybrid. Diff: --- gcc/auto-inc-dec.c | 53 ++++++----- gcc/config/aarch64/aarch64-morello.md | 2 +- gcc/config/aarch64/aarch64.c | 12 ++- gcc/rtlanal.c | 5 +- .../aarch64/morello/alt-base-autoinc-cadi-1.c | 23 +++++ .../aarch64/morello/alt-base-autoinc-df-1.c | 21 +++++ .../aarch64/morello/alt-base-autoinc-di-1.c | 21 +++++ .../aarch64/morello/alt-base-autoinc-hf-1.c | 23 +++++ .../aarch64/morello/alt-base-autoinc-hi-1.c | 21 +++++ .../aarch64/morello/alt-base-autoinc-qi-1.c | 21 +++++ .../aarch64/morello/alt-base-autoinc-sf-1.c | 21 +++++ .../aarch64/morello/alt-base-autoinc-si-1.c | 21 +++++ .../gcc.target/aarch64/morello/load-store-utils.h | 33 +++++++ .../aarch64/morello/normal-base-autoinc-cadi-1.c | 84 +++++++++++++++++ .../aarch64/morello/normal-base-autoinc-cadi-2.c | 102 ++++++++++++++++++++ .../aarch64/morello/normal-base-autoinc-df-1.c | 101 ++++++++++++++++++++ .../aarch64/morello/normal-base-autoinc-di-1.c | 101 ++++++++++++++++++++ .../aarch64/morello/normal-base-autoinc-hf-1.c | 103 +++++++++++++++++++++ .../aarch64/morello/normal-base-autoinc-hi-1.c | 101 ++++++++++++++++++++ .../aarch64/morello/normal-base-autoinc-qi-1.c | 101 ++++++++++++++++++++ .../aarch64/morello/normal-base-autoinc-sf-1.c | 101 ++++++++++++++++++++ .../aarch64/morello/normal-base-autoinc-si-1.c | 101 ++++++++++++++++++++ 22 files changed, 1145 insertions(+), 27 deletions(-) diff --git a/gcc/auto-inc-dec.c b/gcc/auto-inc-dec.c index 38be4c98484..2ff9a198de1 100644 --- a/gcc/auto-inc-dec.c +++ b/gcc/auto-inc-dec.c @@ -448,6 +448,16 @@ move_dead_notes (rtx_insn *to_insn, rtx_insn *from_insn, rtx pattern) } } +/* Add address offset DELTA_REG to base address BASE_REG, both of which + are known to be registers. */ + +static rtx +plus_reg (rtx base_reg, rtx delta_reg) +{ + return gen_pointer_plus (as_a (GET_MODE (base_reg)), + base_reg, delta_reg); +} + /* Change mem_insn.mem_loc so that uses NEW_ADDR which has an increment of INC_REG. To have reached this point, the change is a legitimate one from a dataflow point of view. The only questions @@ -543,8 +553,7 @@ attempt_change (rtx new_addr, rtx inc_reg) if (reg_next_debug_use && reg_next_debug_use[regno] && BLOCK_FOR_INSN (reg_next_debug_use[regno]) == bb) { - rtx adjres = gen_rtx_PLUS (GET_MODE (inc_insn.reg_res), - inc_insn.reg_res, inc_insn.reg1); + rtx adjres = plus_reg (inc_insn.reg_res, inc_insn.reg1); if (dump_file) fprintf (dump_file, "adjusting debug insns\n"); propagate_for_debug (PREV_INSN (reg_next_debug_use[regno]), @@ -574,7 +583,11 @@ attempt_change (rtx new_addr, rtx inc_reg) case FORM_POST_INC: regno = REGNO (inc_insn.reg_res); if (reg_next_debug_use && reg_next_debug_use[regno] - && BLOCK_FOR_INSN (reg_next_debug_use[regno]) == bb) + && BLOCK_FOR_INSN (reg_next_debug_use[regno]) == bb + /* Currently no capability target supports pre/post subtraction + of a register, so we don't need to find a valid representation + of it. */ + && !CAPABILITY_MODE_P (GET_MODE (inc_insn.reg_res))) { rtx adjres = gen_rtx_MINUS (GET_MODE (inc_insn.reg_res), inc_insn.reg_res, inc_insn.reg1); @@ -597,8 +610,7 @@ attempt_change (rtx new_addr, rtx inc_reg) if (reg_next_debug_use && reg_next_debug_use[regno] && BLOCK_FOR_INSN (reg_next_debug_use[regno]) == bb) { - rtx adjres = gen_rtx_PLUS (GET_MODE (inc_insn.reg_res), - inc_insn.reg_res, inc_insn.reg1); + rtx adjres = plus_reg (inc_insn.reg_res, inc_insn.reg1); if (dump_file) fprintf (dump_file, "adjusting debug insns\n"); propagate_for_debug (PREV_INSN (reg_next_debug_use[regno]), @@ -778,9 +790,8 @@ try_merge (void) fprintf (dump_file, "trying DISP_PRE\n"); return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, inc_reg, - gen_rtx_PLUS (reg_mode, - inc_reg, - inc_insn.reg1)), + plus_reg (inc_reg, + inc_insn.reg1)), inc_reg); case DISP_POST: /* con++ */ @@ -788,9 +799,8 @@ try_merge (void) fprintf (dump_file, "trying POST_DISP\n"); return attempt_change (gen_rtx_POST_MODIFY (reg_mode, inc_reg, - gen_rtx_PLUS (reg_mode, - inc_reg, - inc_insn.reg1)), + plus_reg (inc_reg, + inc_insn.reg1)), inc_reg); case REG_PRE: /* ++reg */ @@ -798,9 +808,8 @@ try_merge (void) fprintf (dump_file, "trying PRE_REG\n"); return attempt_change (gen_rtx_PRE_MODIFY (reg_mode, inc_reg, - gen_rtx_PLUS (reg_mode, - inc_reg, - inc_insn.reg1)), + plus_reg (inc_reg, + inc_insn.reg1)), inc_reg); case REG_POST: /* reg++ */ @@ -808,9 +817,8 @@ try_merge (void) fprintf (dump_file, "trying POST_REG\n"); return attempt_change (gen_rtx_POST_MODIFY (reg_mode, inc_reg, - gen_rtx_PLUS (reg_mode, - inc_reg, - inc_insn.reg1)), + plus_reg (inc_reg, + inc_insn.reg1)), inc_reg); } } @@ -856,7 +864,7 @@ parse_add_or_inc (rtx_insn *insn, bool before_mem) if (!REG_P (SET_DEST (pat))) return false; - if ((GET_CODE (SET_SRC (pat)) != PLUS) + if (!any_plus_p (SET_SRC (pat)) && (GET_CODE (SET_SRC (pat)) != MINUS)) return false; @@ -882,7 +890,7 @@ parse_add_or_inc (rtx_insn *insn, bool before_mem) { /* Process a = b + c where c is a const. */ inc_insn.reg1_is_const = true; - if (GET_CODE (SET_SRC (pat)) == PLUS) + if (any_plus_p (SET_SRC (pat))) { inc_insn.reg1 = XEXP (SET_SRC (pat), 1); inc_insn.reg1_val = INTVAL (inc_insn.reg1); @@ -896,7 +904,7 @@ parse_add_or_inc (rtx_insn *insn, bool before_mem) } else if ((HAVE_PRE_MODIFY_REG || HAVE_POST_MODIFY_REG) && (REG_P (XEXP (SET_SRC (pat), 1))) - && GET_CODE (SET_SRC (pat)) == PLUS) + && any_plus_p (SET_SRC (pat))) { /* Process a = b + c where c is a reg. */ inc_insn.reg1 = XEXP (SET_SRC (pat), 1); @@ -965,7 +973,7 @@ find_address (rtx *address_of_x, rtx findreg) return -1; } if (code == MEM && findreg == inc_insn.reg_res - && GET_CODE (XEXP (x, 0)) == PLUS + && any_plus_p (XEXP (x, 0)) && rtx_equal_p (XEXP (XEXP (x, 0), 0), inc_insn.reg_res)) { rtx b = XEXP (XEXP (x, 0), 1); @@ -1355,7 +1363,8 @@ find_mem (rtx *address_of_x) if (find_inc (true)) return true; } - if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS + if (code == MEM + && any_plus_p (XEXP (x, 0)) && REG_P (XEXP (XEXP (x, 0), 0))) { rtx reg1 = XEXP (XEXP (x, 0), 1); diff --git a/gcc/config/aarch64/aarch64-morello.md b/gcc/config/aarch64/aarch64-morello.md index 3ca049c14c8..a21005ee25a 100644 --- a/gcc/config/aarch64/aarch64-morello.md +++ b/gcc/config/aarch64/aarch64-morello.md @@ -149,7 +149,7 @@ mov\\t%0, %1 mov\\t%0, xzr ldr\\t%0, %1 - str\\t%1, %0 + str\\t%x1, %0 adr\\t%0, %c1 adrp\\t%0, %A1" ) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 1bb5cb6ce86..f1f8624f455 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -9813,6 +9813,10 @@ aarch64_classify_address (struct aarch64_address_info *info, && (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)))); + /* There are no alternative-base pre-modify or post-modify forms. */ + if (alt_base_p && GET_RTX_CLASS (code) == RTX_AUTOINC) + return false; + /* For SVE, only accept [Rn], [Rn, Rm, LSL #shift] and [Rn, #offset, MUL VL]. */ if ((vec_flags & (VEC_SVE_DATA | VEC_SVE_PRED)) != 0 @@ -9954,8 +9958,12 @@ aarch64_classify_address (struct aarch64_address_info *info, if (ldr_str_mode != VOIDmode) { gcc_assert (known_eq (ldr_str_offset, 0)); - if (!aarch64_offset_9bit_signed_unscaled_p (ldr_str_mode, - offset)) + /* The pre/post-modify forms of LDR/STR Cn require a + multiple of 16. */ + if (TARGET_MORELLO && ldr_str_mode == CADImode + ? !offset_9bit_signed_scaled_p (ldr_str_mode, offset) + : !aarch64_offset_9bit_signed_unscaled_p (ldr_str_mode, + offset)) return false; } diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 72550069b2e..fdef6b0cdb0 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -3383,6 +3383,7 @@ computed_jump_p (const rtx_insn *insn) static int for_each_inc_dec_find_inc_dec (rtx mem, for_each_inc_dec_fn fn, void *data) { + auto addr_mode = mem_address_mode (mem); rtx x = XEXP (mem, 0); switch (GET_CODE (x)) { @@ -3391,7 +3392,7 @@ for_each_inc_dec_find_inc_dec (rtx mem, for_each_inc_dec_fn fn, void *data) { poly_int64 size = GET_MODE_SIZE (GET_MODE (mem)); rtx r1 = XEXP (x, 0); - rtx c = gen_int_mode (size, GET_MODE (r1)); + rtx c = gen_int_mode (size, offset_mode (addr_mode)); return fn (mem, x, r1, r1, c, data); } @@ -3400,7 +3401,7 @@ for_each_inc_dec_find_inc_dec (rtx mem, for_each_inc_dec_fn fn, void *data) { poly_int64 size = GET_MODE_SIZE (GET_MODE (mem)); rtx r1 = XEXP (x, 0); - rtx c = gen_int_mode (-size, GET_MODE (r1)); + rtx c = gen_int_mode (-size, offset_mode (addr_mode)); return fn (mem, x, r1, r1, c, data); } diff --git a/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-cadi-1.c b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-cadi-1.c new file mode 100644 index 00000000000..838c3868907 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-cadi-1.c @@ -0,0 +1,23 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-skip-if "" { *-*-* } { "-mabi=purecap" "-mfake-capability" } { "" } } */ + +#define ALT_BASE +#include "load-store-utils.h" + +typedef __uintcap_t uintcap_t; + +PRE_MODIFY_OFFSET (uintcap_t, m17) +PRE_MODIFY_OFFSET (uintcap_t, m16) +PRE_MODIFY_OFFSET (uintcap_t, m1) +PRE_MODIFY_OFFSET (uintcap_t, 1) +PRE_MODIFY_OFFSET (uintcap_t, 15) +PRE_MODIFY_OFFSET (uintcap_t, 16) +POST_MODIFY_OFFSET (uintcap_t, m17) +POST_MODIFY_OFFSET (uintcap_t, m16) +POST_MODIFY_OFFSET (uintcap_t, m1) +POST_MODIFY_OFFSET (uintcap_t, 1) +POST_MODIFY_OFFSET (uintcap_t, 15) +POST_MODIFY_OFFSET (uintcap_t, 16) + +/* { dg-final { scan-assembler-not {c[0-9]+\][!,]} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-df-1.c b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-df-1.c new file mode 100644 index 00000000000..c626973620f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-df-1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-skip-if "" { *-*-* } { "-mabi=purecap" "-mfake-capability" } { "" } } */ + +#define ALT_BASE +#include "load-store-utils.h" + +PRE_MODIFY_OFFSET (double, m33) +PRE_MODIFY_OFFSET (double, m32) +PRE_MODIFY_OFFSET (double, m1) +PRE_MODIFY_OFFSET (double, 1) +PRE_MODIFY_OFFSET (double, 31) +PRE_MODIFY_OFFSET (double, 32) +POST_MODIFY_OFFSET (double, m33) +POST_MODIFY_OFFSET (double, m32) +POST_MODIFY_OFFSET (double, m1) +POST_MODIFY_OFFSET (double, 1) +POST_MODIFY_OFFSET (double, 31) +POST_MODIFY_OFFSET (double, 32) + +/* { dg-final { scan-assembler-not {c[0-9]+\][!,]} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-di-1.c b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-di-1.c new file mode 100644 index 00000000000..e4e6ea7842a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-di-1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-skip-if "" { *-*-* } { "-mabi=purecap" "-mfake-capability" } { "" } } */ + +#define ALT_BASE +#include "load-store-utils.h" + +PRE_MODIFY_OFFSET (uint64_t, m33) +PRE_MODIFY_OFFSET (uint64_t, m32) +PRE_MODIFY_OFFSET (uint64_t, m1) +PRE_MODIFY_OFFSET (uint64_t, 1) +PRE_MODIFY_OFFSET (uint64_t, 31) +PRE_MODIFY_OFFSET (uint64_t, 32) +POST_MODIFY_OFFSET (uint64_t, m33) +POST_MODIFY_OFFSET (uint64_t, m32) +POST_MODIFY_OFFSET (uint64_t, m1) +POST_MODIFY_OFFSET (uint64_t, 1) +POST_MODIFY_OFFSET (uint64_t, 31) +POST_MODIFY_OFFSET (uint64_t, 32) + +/* { dg-final { scan-assembler-not {\][!,]} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-hf-1.c b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-hf-1.c new file mode 100644 index 00000000000..8ec45381870 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-hf-1.c @@ -0,0 +1,23 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-skip-if "" { *-*-* } { "-mabi=purecap" "-mfake-capability" } { "" } } */ + +#define ALT_BASE +#include "load-store-utils.h" + +typedef __fp16 fp16; + +PRE_MODIFY_OFFSET (fp16, m129) +PRE_MODIFY_OFFSET (fp16, m128) +PRE_MODIFY_OFFSET (fp16, m1) +PRE_MODIFY_OFFSET (fp16, 1) +PRE_MODIFY_OFFSET (fp16, 127) +PRE_MODIFY_OFFSET (fp16, 128) +POST_MODIFY_OFFSET (fp16, m129) +POST_MODIFY_OFFSET (fp16, m128) +POST_MODIFY_OFFSET (fp16, m1) +POST_MODIFY_OFFSET (fp16, 1) +POST_MODIFY_OFFSET (fp16, 127) +POST_MODIFY_OFFSET (fp16, 128) + +/* { dg-final { scan-assembler-not {c[0-9]+\][!,]} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-hi-1.c b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-hi-1.c new file mode 100644 index 00000000000..b370a8e6ee2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-hi-1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-skip-if "" { *-*-* } { "-mabi=purecap" "-mfake-capability" } { "" } } */ + +#define ALT_BASE +#include "load-store-utils.h" + +PRE_MODIFY_OFFSET (uint16_t, m129) +PRE_MODIFY_OFFSET (uint16_t, m128) +PRE_MODIFY_OFFSET (uint16_t, m1) +PRE_MODIFY_OFFSET (uint16_t, 1) +PRE_MODIFY_OFFSET (uint16_t, 127) +PRE_MODIFY_OFFSET (uint16_t, 128) +POST_MODIFY_OFFSET (uint16_t, m129) +POST_MODIFY_OFFSET (uint16_t, m128) +POST_MODIFY_OFFSET (uint16_t, m1) +POST_MODIFY_OFFSET (uint16_t, 1) +POST_MODIFY_OFFSET (uint16_t, 127) +POST_MODIFY_OFFSET (uint16_t, 128) + +/* { dg-final { scan-assembler-not {\][!,]} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-qi-1.c b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-qi-1.c new file mode 100644 index 00000000000..be59146e4bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-qi-1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-skip-if "" { *-*-* } { "-mabi=purecap" "-mfake-capability" } { "" } } */ + +#define ALT_BASE +#include "load-store-utils.h" + +PRE_MODIFY_OFFSET (uint8_t, m257) +PRE_MODIFY_OFFSET (uint8_t, m256) +PRE_MODIFY_OFFSET (uint8_t, m1) +PRE_MODIFY_OFFSET (uint8_t, 1) +PRE_MODIFY_OFFSET (uint8_t, 255) +PRE_MODIFY_OFFSET (uint8_t, 256) +POST_MODIFY_OFFSET (uint8_t, m257) +POST_MODIFY_OFFSET (uint8_t, m256) +POST_MODIFY_OFFSET (uint8_t, m1) +POST_MODIFY_OFFSET (uint8_t, 1) +POST_MODIFY_OFFSET (uint8_t, 255) +POST_MODIFY_OFFSET (uint8_t, 256) + +/* { dg-final { scan-assembler-not {\][!,]} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-sf-1.c b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-sf-1.c new file mode 100644 index 00000000000..a6e0148968f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-sf-1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-skip-if "" { *-*-* } { "-mabi=purecap" "-mfake-capability" } { "" } } */ + +#define ALT_BASE +#include "load-store-utils.h" + +PRE_MODIFY_OFFSET (float, m65) +PRE_MODIFY_OFFSET (float, m64) +PRE_MODIFY_OFFSET (float, m1) +PRE_MODIFY_OFFSET (float, 1) +PRE_MODIFY_OFFSET (float, 63) +PRE_MODIFY_OFFSET (float, 64) +POST_MODIFY_OFFSET (float, m65) +POST_MODIFY_OFFSET (float, m64) +POST_MODIFY_OFFSET (float, m1) +POST_MODIFY_OFFSET (float, 1) +POST_MODIFY_OFFSET (float, 63) +POST_MODIFY_OFFSET (float, 64) + +/* { dg-final { scan-assembler-not {c[0-9]+\][!,]} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-si-1.c b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-si-1.c new file mode 100644 index 00000000000..4126356db2f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/alt-base-autoinc-si-1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-skip-if "" { *-*-* } { "-mabi=purecap" "-mfake-capability" } { "" } } */ + +#define ALT_BASE +#include "load-store-utils.h" + +PRE_MODIFY_OFFSET (uint32_t, m65) +PRE_MODIFY_OFFSET (uint32_t, m64) +PRE_MODIFY_OFFSET (uint32_t, m1) +PRE_MODIFY_OFFSET (uint32_t, 1) +PRE_MODIFY_OFFSET (uint32_t, 63) +PRE_MODIFY_OFFSET (uint32_t, 64) +POST_MODIFY_OFFSET (uint32_t, m65) +POST_MODIFY_OFFSET (uint32_t, m64) +POST_MODIFY_OFFSET (uint32_t, m1) +POST_MODIFY_OFFSET (uint32_t, 1) +POST_MODIFY_OFFSET (uint32_t, 63) +POST_MODIFY_OFFSET (uint32_t, 64) + +/* { dg-final { scan-assembler-not {\][!,]} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/morello/load-store-utils.h b/gcc/testsuite/gcc.target/aarch64/morello/load-store-utils.h index 22dae5e9649..bd88bef99cf 100644 --- a/gcc/testsuite/gcc.target/aarch64/morello/load-store-utils.h +++ b/gcc/testsuite/gcc.target/aarch64/morello/load-store-utils.h @@ -17,6 +17,13 @@ #define m254 -254 #define m252 -252 #define m248 -248 +#define m129 -129 +#define m128 -128 +#define m65 -65 +#define m64 -64 +#define m33 -33 +#define m32 -32 +#define m17 -17 #define m16 -16 #define m8 -8 #define m4 -4 @@ -94,3 +101,29 @@ TYPE *CAP ptr = (TYPE *CAP) (base + byte_index); \ *ptr = 0; \ } + +#define PRE_MODIFY_OFFSET(TYPE, OFFSET) \ + void \ + pre_modify_##TYPE##_##OFFSET (TYPE *CAP ptr, TYPE *CAP end, TYPE x) \ + { \ + do \ + { \ + ptr += OFFSET; \ + *ptr = x; \ + x += 1; \ + } \ + while (ptr != end); \ + } + +#define POST_MODIFY_OFFSET(TYPE, OFFSET) \ + void \ + post_modify_##TYPE##_##OFFSET (TYPE *CAP ptr, TYPE *CAP end, TYPE x) \ + { \ + do \ + { \ + *ptr = x; \ + ptr += OFFSET; \ + x += 1; \ + } \ + while (ptr != end); \ + } diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-cadi-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-cadi-1.c new file mode 100644 index 00000000000..78b7f020ae4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-cadi-1.c @@ -0,0 +1,84 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ +/* { dg-skip-if "" { *-*-* } { "-mfake-capability" } { "" } } */ + +#include "load-store-utils.h" + +typedef __uintcap_t uintcap_t; + +/* Must assemble correctly, but don't require a specific sequence. */ +PRE_MODIFY_OFFSET (uintcap_t, m257) + +/* +** pre_modify_uintcap_t_m256: +** ... +** str c[0-9]+, \[[xc][0-9]+, #?-4096\]! +** ... +*/ +PRE_MODIFY_OFFSET (uintcap_t, m256) + +/* +** pre_modify_uintcap_t_m1: +** ... +** str c[0-9]+, \[[xc][0-9]+, #?-16\]! +** ... +*/ +PRE_MODIFY_OFFSET (uintcap_t, m1) + +/* +** pre_modify_uintcap_t_1: +** ... +** str c[0-9]+, \[[xc][0-9]+, #?16\]! +** ... +*/ +PRE_MODIFY_OFFSET (uintcap_t, 1) + +/* +** pre_modify_uintcap_t_255: +** ... +** str c[0-9]+, \[[xc][0-9]+, #?4080\]! +** ... +*/ +PRE_MODIFY_OFFSET (uintcap_t, 255) + +/* Must assemble correctly, but don't require a specific sequence. */ +PRE_MODIFY_OFFSET (uintcap_t, 16) + +/* Must assemble correctly, but don't require a specific sequence. */ +POST_MODIFY_OFFSET (uintcap_t, m257) + +/* +** post_modify_uintcap_t_m256: +** ... +** str c[0-9]+, \[[xc][0-9]+\], #?-4096 +** ... +*/ +POST_MODIFY_OFFSET (uintcap_t, m256) + +/* +** post_modify_uintcap_t_m1: +** ... +** str c[0-9]+, \[[xc][0-9]+\], #?-16 +** ... +*/ +POST_MODIFY_OFFSET (uintcap_t, m1) + +/* +** post_modify_uintcap_t_1: +** ... +** str c[0-9]+, \[[xc][0-9]+\], #?16 +** ... +*/ +POST_MODIFY_OFFSET (uintcap_t, 1) + +/* +** post_modify_uintcap_t_255: +** ... +** str c[0-9]+, \[[xc][0-9]+\], #?4080 +** ... +*/ +POST_MODIFY_OFFSET (uintcap_t, 255) + +/* Must assemble correctly, but don't require a specific sequence. */ +POST_MODIFY_OFFSET (uintcap_t, 256) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-cadi-2.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-cadi-2.c new file mode 100644 index 00000000000..25c784f3297 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-cadi-2.c @@ -0,0 +1,102 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ +/* { dg-skip-if "" { *-*-* } { "*" } { "-mfake-capability" } } */ + +#include "load-store-utils.h" + +/* +** pre_modify_uint64_t_m33: +** ... +** sub .*, #?264 +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, m33) + +/* +** pre_modify_uint64_t_m32: +** ... +** str x[0-9]+, \[x[0-9]+, #?-256\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, m32) + +/* +** pre_modify_uint64_t_m1: +** ... +** str x[0-9]+, \[x[0-9]+, #?-8\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, m1) + +/* +** pre_modify_uint64_t_1: +** ... +** str x[0-9]+, \[x[0-9]+, #?8\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, 1) + +/* +** pre_modify_uint64_t_31: +** ... +** str x[0-9]+, \[x[0-9]+, #?248\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, 31) + +/* +** pre_modify_uint64_t_32: +** ... +** add .*, #?256 +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, 32) + +/* +** post_modify_uint64_t_m33: +** ... +** sub .*, #?264 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, m33) + +/* +** post_modify_uint64_t_m32: +** ... +** str x[0-9]+, \[x[0-9]+\], #?-256 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, m32) + +/* +** post_modify_uint64_t_m1: +** ... +** str x[0-9]+, \[x[0-9]+\], #?-8 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, m1) + +/* +** post_modify_uint64_t_1: +** ... +** str x[0-9]+, \[x[0-9]+\], #?8 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, 1) + +/* +** post_modify_uint64_t_31: +** ... +** str x[0-9]+, \[x[0-9]+\], #?248 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, 31) + +/* +** post_modify_uint64_t_32: +** ... +** add .*, #?256 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, 32) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-df-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-df-1.c new file mode 100644 index 00000000000..3fc41b7fad8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-df-1.c @@ -0,0 +1,101 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ + +#include "load-store-utils.h" + +/* +** pre_modify_double_m33: +** ... +** sub .*, #?264 +** ... +*/ +PRE_MODIFY_OFFSET (double, m33) + +/* +** pre_modify_double_m32: +** ... +** str d[0-9]+, \[[xc][0-9]+, #?-256\]! +** ... +*/ +PRE_MODIFY_OFFSET (double, m32) + +/* +** pre_modify_double_m1: +** ... +** str d[0-9]+, \[[xc][0-9]+, #?-8\]! +** ... +*/ +PRE_MODIFY_OFFSET (double, m1) + +/* +** pre_modify_double_1: +** ... +** str d[0-9]+, \[[xc][0-9]+, #?8\]! +** ... +*/ +PRE_MODIFY_OFFSET (double, 1) + +/* +** pre_modify_double_31: +** ... +** str d[0-9]+, \[[xc][0-9]+, #?248\]! +** ... +*/ +PRE_MODIFY_OFFSET (double, 31) + +/* +** pre_modify_double_32: +** ... +** add .*, #?256 +** ... +*/ +PRE_MODIFY_OFFSET (double, 32) + +/* +** post_modify_double_m33: +** ... +** sub .*, #?264 +** ... +*/ +POST_MODIFY_OFFSET (double, m33) + +/* +** post_modify_double_m32: +** ... +** str d[0-9]+, \[[xc][0-9]+\], #?-256 +** ... +*/ +POST_MODIFY_OFFSET (double, m32) + +/* +** post_modify_double_m1: +** ... +** str d[0-9]+, \[[xc][0-9]+\], #?-8 +** ... +*/ +POST_MODIFY_OFFSET (double, m1) + +/* +** post_modify_double_1: +** ... +** str d[0-9]+, \[[xc][0-9]+\], #?8 +** ... +*/ +POST_MODIFY_OFFSET (double, 1) + +/* +** post_modify_double_31: +** ... +** str d[0-9]+, \[[xc][0-9]+\], #?248 +** ... +*/ +POST_MODIFY_OFFSET (double, 31) + +/* +** post_modify_double_32: +** ... +** add .*, #?256 +** ... +*/ +POST_MODIFY_OFFSET (double, 32) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-di-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-di-1.c new file mode 100644 index 00000000000..fca16434388 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-di-1.c @@ -0,0 +1,101 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-fno-ivopts -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ + +#include "load-store-utils.h" + +/* +** pre_modify_uint64_t_m33: +** ... +** sub .*, #?264 +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, m33) + +/* +** pre_modify_uint64_t_m32: +** ... +** str x[0-9]+, \[[xc][0-9]+, #?-256\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, m32) + +/* +** pre_modify_uint64_t_m1: +** ... +** str x[0-9]+, \[[xc][0-9]+, #?-8\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, m1) + +/* +** pre_modify_uint64_t_1: +** ... +** str x[0-9]+, \[[xc][0-9]+, #?8\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, 1) + +/* +** pre_modify_uint64_t_31: +** ... +** str x[0-9]+, \[[xc][0-9]+, #?248\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, 31) + +/* +** pre_modify_uint64_t_32: +** ... +** add .*, #?256 +** ... +*/ +PRE_MODIFY_OFFSET (uint64_t, 32) + +/* +** post_modify_uint64_t_m33: +** ... +** sub .*, #?264 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, m33) + +/* +** post_modify_uint64_t_m32: +** ... +** str x[0-9]+, \[[xc][0-9]+\], #?-256 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, m32) + +/* +** post_modify_uint64_t_m1: +** ... +** str x[0-9]+, \[[xc][0-9]+\], #?-8 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, m1) + +/* +** post_modify_uint64_t_1: +** ... +** str x[0-9]+, \[[xc][0-9]+\], #?8 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, 1) + +/* +** post_modify_uint64_t_31: +** ... +** str x[0-9]+, \[[xc][0-9]+\], #?248 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, 31) + +/* +** post_modify_uint64_t_32: +** ... +** add .*, #?256 +** ... +*/ +POST_MODIFY_OFFSET (uint64_t, 32) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-hf-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-hf-1.c new file mode 100644 index 00000000000..15296d4c6a4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-hf-1.c @@ -0,0 +1,103 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ + +#include "load-store-utils.h" + +typedef __fp16 fp16; + +/* +** pre_modify_fp16_m129: +** ... +** sub .*, #?258 +** ... +*/ +PRE_MODIFY_OFFSET (fp16, m129) + +/* +** pre_modify_fp16_m128: +** ... +** str h[0-9]+, \[[xc][0-9]+, #?-256\]! +** ... +*/ +PRE_MODIFY_OFFSET (fp16, m128) + +/* +** pre_modify_fp16_m1: +** ... +** str h[0-9]+, \[[xc][0-9]+, #?-2\]! +** ... +*/ +PRE_MODIFY_OFFSET (fp16, m1) + +/* +** pre_modify_fp16_1: +** ... +** str h[0-9]+, \[[xc][0-9]+, #?2\]! +** ... +*/ +PRE_MODIFY_OFFSET (fp16, 1) + +/* +** pre_modify_fp16_127: +** ... +** str h[0-9]+, \[[xc][0-9]+, #?254\]! +** ... +*/ +PRE_MODIFY_OFFSET (fp16, 127) + +/* +** pre_modify_fp16_128: +** ... +** add .*, #?256 +** ... +*/ +PRE_MODIFY_OFFSET (fp16, 128) + +/* +** post_modify_fp16_m129: +** ... +** sub .*, #?258 +** ... +*/ +POST_MODIFY_OFFSET (fp16, m129) + +/* +** post_modify_fp16_m128: +** ... +** str h[0-9]+, \[[xc][0-9]+\], #?-256 +** ... +*/ +POST_MODIFY_OFFSET (fp16, m128) + +/* +** post_modify_fp16_m1: +** ... +** str h[0-9]+, \[[xc][0-9]+\], #?-2 +** ... +*/ +POST_MODIFY_OFFSET (fp16, m1) + +/* +** post_modify_fp16_1: +** ... +** str h[0-9]+, \[[xc][0-9]+\], #?2 +** ... +*/ +POST_MODIFY_OFFSET (fp16, 1) + +/* +** post_modify_fp16_127: +** ... +** str h[0-9]+, \[[xc][0-9]+\], #?254 +** ... +*/ +POST_MODIFY_OFFSET (fp16, 127) + +/* +** post_modify_fp16_128: +** ... +** add .*, #?256 +** ... +*/ +POST_MODIFY_OFFSET (fp16, 128) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-hi-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-hi-1.c new file mode 100644 index 00000000000..08e4b611789 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-hi-1.c @@ -0,0 +1,101 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ + +#include "load-store-utils.h" + +/* +** pre_modify_uint16_t_m129: +** ... +** sub .*, #?258 +** ... +*/ +PRE_MODIFY_OFFSET (uint16_t, m129) + +/* +** pre_modify_uint16_t_m128: +** ... +** strh w[0-9]+, \[[xc][0-9]+, #?-256\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint16_t, m128) + +/* +** pre_modify_uint16_t_m1: +** ... +** strh w[0-9]+, \[[xc][0-9]+, #?-2\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint16_t, m1) + +/* +** pre_modify_uint16_t_1: +** ... +** strh w[0-9]+, \[[xc][0-9]+, #?2\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint16_t, 1) + +/* +** pre_modify_uint16_t_127: +** ... +** strh w[0-9]+, \[[xc][0-9]+, #?254\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint16_t, 127) + +/* +** pre_modify_uint16_t_128: +** ... +** add .*, #?256 +** ... +*/ +PRE_MODIFY_OFFSET (uint16_t, 128) + +/* +** post_modify_uint16_t_m129: +** ... +** sub .*, #?258 +** ... +*/ +POST_MODIFY_OFFSET (uint16_t, m129) + +/* +** post_modify_uint16_t_m128: +** ... +** strh w[0-9]+, \[[xc][0-9]+\], #?-256 +** ... +*/ +POST_MODIFY_OFFSET (uint16_t, m128) + +/* +** post_modify_uint16_t_m1: +** ... +** strh w[0-9]+, \[[xc][0-9]+\], #?-2 +** ... +*/ +POST_MODIFY_OFFSET (uint16_t, m1) + +/* +** post_modify_uint16_t_1: +** ... +** strh w[0-9]+, \[[xc][0-9]+\], #?2 +** ... +*/ +POST_MODIFY_OFFSET (uint16_t, 1) + +/* +** post_modify_uint16_t_127: +** ... +** strh w[0-9]+, \[[xc][0-9]+\], #?254 +** ... +*/ +POST_MODIFY_OFFSET (uint16_t, 127) + +/* +** post_modify_uint16_t_128: +** ... +** add .*, #?256 +** ... +*/ +POST_MODIFY_OFFSET (uint16_t, 128) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-qi-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-qi-1.c new file mode 100644 index 00000000000..8ace6c812a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-qi-1.c @@ -0,0 +1,101 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ + +#include "load-store-utils.h" + +/* +** pre_modify_uint8_t_m257: +** ... +** sub .*, #?257 +** ... +*/ +PRE_MODIFY_OFFSET (uint8_t, m257) + +/* +** pre_modify_uint8_t_m256: +** ... +** strb w[0-9]+, \[[xc][0-9]+, #?-256\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint8_t, m256) + +/* +** pre_modify_uint8_t_m1: +** ... +** strb w[0-9]+, \[[xc][0-9]+, #?-1\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint8_t, m1) + +/* +** pre_modify_uint8_t_1: +** ... +** strb w[0-9]+, \[[xc][0-9]+, #?1\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint8_t, 1) + +/* +** pre_modify_uint8_t_255: +** ... +** strb w[0-9]+, \[[xc][0-9]+, #?255\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint8_t, 255) + +/* +** pre_modify_uint8_t_256: +** ... +** add .*, #?256 +** ... +*/ +PRE_MODIFY_OFFSET (uint8_t, 256) + +/* +** post_modify_uint8_t_m257: +** ... +** sub .*, #?257 +** ... +*/ +POST_MODIFY_OFFSET (uint8_t, m257) + +/* +** post_modify_uint8_t_m256: +** ... +** strb w[0-9]+, \[[xc][0-9]+\], #?-256 +** ... +*/ +POST_MODIFY_OFFSET (uint8_t, m256) + +/* +** post_modify_uint8_t_m1: +** ... +** strb w[0-9]+, \[[xc][0-9]+\], #?-1 +** ... +*/ +POST_MODIFY_OFFSET (uint8_t, m1) + +/* +** post_modify_uint8_t_1: +** ... +** strb w[0-9]+, \[[xc][0-9]+\], #?1 +** ... +*/ +POST_MODIFY_OFFSET (uint8_t, 1) + +/* +** post_modify_uint8_t_255: +** ... +** strb w[0-9]+, \[[xc][0-9]+\], #?255 +** ... +*/ +POST_MODIFY_OFFSET (uint8_t, 255) + +/* +** post_modify_uint8_t_256: +** ... +** add .*, #?256 +** ... +*/ +POST_MODIFY_OFFSET (uint8_t, 256) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-sf-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-sf-1.c new file mode 100644 index 00000000000..8b6857b58bd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-sf-1.c @@ -0,0 +1,101 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ + +#include "load-store-utils.h" + +/* +** pre_modify_float_m65: +** ... +** sub .*, #?260 +** ... +*/ +PRE_MODIFY_OFFSET (float, m65) + +/* +** pre_modify_float_m64: +** ... +** str s[0-9]+, \[[xc][0-9]+, #?-256\]! +** ... +*/ +PRE_MODIFY_OFFSET (float, m64) + +/* +** pre_modify_float_m1: +** ... +** str s[0-9]+, \[[xc][0-9]+, #?-4\]! +** ... +*/ +PRE_MODIFY_OFFSET (float, m1) + +/* +** pre_modify_float_1: +** ... +** str s[0-9]+, \[[xc][0-9]+, #?4\]! +** ... +*/ +PRE_MODIFY_OFFSET (float, 1) + +/* +** pre_modify_float_63: +** ... +** str s[0-9]+, \[[xc][0-9]+, #?252\]! +** ... +*/ +PRE_MODIFY_OFFSET (float, 63) + +/* +** pre_modify_float_64: +** ... +** add .*, #?256 +** ... +*/ +PRE_MODIFY_OFFSET (float, 64) + +/* +** post_modify_float_m65: +** ... +** sub .*, #?260 +** ... +*/ +POST_MODIFY_OFFSET (float, m65) + +/* +** post_modify_float_m64: +** ... +** str s[0-9]+, \[[xc][0-9]+\], #?-256 +** ... +*/ +POST_MODIFY_OFFSET (float, m64) + +/* +** post_modify_float_m1: +** ... +** str s[0-9]+, \[[xc][0-9]+\], #?-4 +** ... +*/ +POST_MODIFY_OFFSET (float, m1) + +/* +** post_modify_float_1: +** ... +** str s[0-9]+, \[[xc][0-9]+\], #?4 +** ... +*/ +POST_MODIFY_OFFSET (float, 1) + +/* +** post_modify_float_63: +** ... +** str s[0-9]+, \[[xc][0-9]+\], #?252 +** ... +*/ +POST_MODIFY_OFFSET (float, 63) + +/* +** post_modify_float_64: +** ... +** add .*, #?256 +** ... +*/ +POST_MODIFY_OFFSET (float, 64) diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-si-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-si-1.c new file mode 100644 index 00000000000..c9d94aa4908 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-autoinc-si-1.c @@ -0,0 +1,101 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ + +#include "load-store-utils.h" + +/* +** pre_modify_uint32_t_m65: +** ... +** sub .*, #?260 +** ... +*/ +PRE_MODIFY_OFFSET (uint32_t, m65) + +/* +** pre_modify_uint32_t_m64: +** ... +** str w[0-9]+, \[[xc][0-9]+, #?-256\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint32_t, m64) + +/* +** pre_modify_uint32_t_m1: +** ... +** str w[0-9]+, \[[xc][0-9]+, #?-4\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint32_t, m1) + +/* +** pre_modify_uint32_t_1: +** ... +** str w[0-9]+, \[[xc][0-9]+, #?4\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint32_t, 1) + +/* +** pre_modify_uint32_t_63: +** ... +** str w[0-9]+, \[[xc][0-9]+, #?252\]! +** ... +*/ +PRE_MODIFY_OFFSET (uint32_t, 63) + +/* +** pre_modify_uint32_t_64: +** ... +** add .*, #?256 +** ... +*/ +PRE_MODIFY_OFFSET (uint32_t, 64) + +/* +** post_modify_uint32_t_m65: +** ... +** sub .*, #?260 +** ... +*/ +POST_MODIFY_OFFSET (uint32_t, m65) + +/* +** post_modify_uint32_t_m64: +** ... +** str w[0-9]+, \[[xc][0-9]+\], #?-256 +** ... +*/ +POST_MODIFY_OFFSET (uint32_t, m64) + +/* +** post_modify_uint32_t_m1: +** ... +** str w[0-9]+, \[[xc][0-9]+\], #?-4 +** ... +*/ +POST_MODIFY_OFFSET (uint32_t, m1) + +/* +** post_modify_uint32_t_1: +** ... +** str w[0-9]+, \[[xc][0-9]+\], #?4 +** ... +*/ +POST_MODIFY_OFFSET (uint32_t, 1) + +/* +** post_modify_uint32_t_63: +** ... +** str w[0-9]+, \[[xc][0-9]+\], #?252 +** ... +*/ +POST_MODIFY_OFFSET (uint32_t, 63) + +/* +** post_modify_uint32_t_64: +** ... +** add .*, #?256 +** ... +*/ +POST_MODIFY_OFFSET (uint32_t, 64)