From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2049) id 4FBE33838034; Fri, 6 May 2022 14:44:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4FBE33838034 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Matthew Malcomson To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/morello)] aarch64: Optimise atomic stores of TI X-Act-Checkin: gcc X-Git-Author: Richard Sandiford X-Git-Refname: refs/vendors/ARM/heads/morello X-Git-Oldrev: ca03be2e923586ea336b5b78d8b58bd5dd825aa9 X-Git-Newrev: e8fe664ab427c2bd31233467f92462c6a46a41b8 Message-Id: <20220506144400.4FBE33838034@sourceware.org> Date: Fri, 6 May 2022 14:44:00 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 May 2022 14:44:00 -0000 https://gcc.gnu.org/g:e8fe664ab427c2bd31233467f92462c6a46a41b8 commit e8fe664ab427c2bd31233467f92462c6a46a41b8 Author: Richard Sandiford Date: Mon Apr 25 19:48:37 2022 +0100 aarch64: Optimise atomic stores of TI Atomic TI stores must be 16-byte aligned. This means that, on Morello, we can implement them using: st... czr, [base] This should be better even for normal-base addresses. However, for alternative-base addresses it has the additional benefit of avoiding an out-of-line function, since there are no alternative-base forms of the atomic pair instructions that TI operations normally use. Diff: --- gcc/config/aarch64/aarch64.c | 2 + gcc/config/aarch64/atomics.md | 15 +++++++ .../morello/normal-base-sync-lock-release-1.c | 50 ++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 4afa004ec1c..5c31ffc52b4 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -20867,6 +20867,8 @@ aarch64_expand_compare_and_swap (rtx operands[]) else emit_move_insn (rval, gen_lowpart (r_mode, oldval)); + if (mode == TImode) + newval = force_reg (mode, newval); emit_insn (gen_aarch64_compare_and_swap_lse (mode, rval, mem, newval, mod_s)); cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, drop_capability (rval), diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md index 79e48cd9f64..4e1646e2791 100644 --- a/gcc/config/aarch64/atomics.md +++ b/gcc/config/aarch64/atomics.md @@ -942,6 +942,21 @@ } ) +(define_expand "atomic_storeti" + [(set (match_operand:TI 0 "aarch64_rcpc_memory_operand") + (unspec_volatile:TI + [(match_operand:TI 1 "const0_operand") + (match_operand:SI 2 "const_int_operand")] ;; model + UNSPECV_STL))] + "TARGET_MORELLO" + { + operands[0] = adjust_address (operands[0], CADImode, 0); + emit_insn (gen_atomic_storecadi (operands[0], CONST0_RTX (CADImode), + operands[2])); + DONE; + } +) + (define_insn "atomic_store" [(set (match_operand:ALLIC 0 "aarch64_rcpc_memory_operand" "=Q,Ust") (unspec_volatile:ALLIC diff --git a/gcc/testsuite/gcc.target/aarch64/morello/normal-base-sync-lock-release-1.c b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-sync-lock-release-1.c new file mode 100644 index 00000000000..38122ac35d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/morello/normal-base-sync-lock-release-1.c @@ -0,0 +1,50 @@ +/* { dg-do assemble } */ +/* { dg-additional-options "-foptimize-sibling-calls -save-temps" } */ +/* { dg-final { check-function-bodies "**" "" { {-O[123s]} } } } */ +/* { dg-skip-if "" { *-*-* } { "-mfake-capability" } { "" } } */ + +#include + +typedef __uint128_t uint128; + +#define TEST_SIZE(TYPE) \ + void \ + test_##TYPE (TYPE *ptr) \ + { \ + __sync_lock_release (ptr); \ + } + +/* +** test_uint8_t: +** stlrb wzr, \[[xc]0\] +** ret +*/ +TEST_SIZE (uint8_t) + +/* +** test_uint16_t: +** stlrh wzr, \[[xc]0\] +** ret +*/ +TEST_SIZE (uint16_t) + +/* +** test_uint32_t: +** stlr wzr, \[[xc]0\] +** ret +*/ +TEST_SIZE (uint32_t) + +/* +** test_uint64_t: +** stlr xzr, \[[xc]0\] +** ret +*/ +TEST_SIZE (uint64_t) + +/* +** test_uint128: +** stlr czr, \[[xc]0\] +** ret +*/ +TEST_SIZE (uint128)