From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2153) id 984DF38425B1; Wed, 11 May 2022 06:20:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 984DF38425B1 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Jakub Jelinek To: gcc-cvs@gcc.gnu.org Subject: [gcc r9-10081] inline-asm: Fix ICE with bitfields in "m" operands [PR100785] X-Act-Checkin: gcc X-Git-Author: Jakub Jelinek X-Git-Refname: refs/heads/releases/gcc-9 X-Git-Oldrev: 80f194b25f573b409ada5761778fb6dfb3cf85e9 X-Git-Newrev: 21a95d88fe628d1da4d59c4eface53503b29a574 Message-Id: <20220511062042.984DF38425B1@sourceware.org> Date: Wed, 11 May 2022 06:20:42 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 May 2022 06:20:42 -0000 https://gcc.gnu.org/g:21a95d88fe628d1da4d59c4eface53503b29a574 commit r9-10081-g21a95d88fe628d1da4d59c4eface53503b29a574 Author: Jakub Jelinek Date: Mon Jun 21 13:30:42 2021 +0200 inline-asm: Fix ICE with bitfields in "m" operands [PR100785] Bitfields, while they live in memory, aren't something inline-asm can easily operate on. For C and "=m" or "+m", we were diagnosing bitfields in the past in the FE, where c_mark_addressable had: case COMPONENT_REF: if (DECL_C_BIT_FIELD (TREE_OPERAND (x, 1))) { error ("cannot take address of bit-field %qD", TREE_OPERAND (x, 1)); return false; } but that check got moved in GCC 6 to build_unary_op instead and now we emit an error during expansion and ICE afterwards (i.e. error-recovery). For "m" it used to be diagnosed in c_mark_addressable too, but since GCC 6 it is ice-on-invalid. For C++, this was never diagnosed in the FE, but used to be diagnosed in the gimplifier and/or during expansion before 4.8. The following patch does multiple things: 1) diagnoses it in the FEs 2) simplifies during expansion the inline asm if any errors have been reported (similarly how e.g. vregs pass if it detects errors on inline-asm either deletes them or simplifies to bare minimum - just labels), so that we don't have error-recovery ICEs there 2021-06-11 Jakub Jelinek PR inline-asm/100785 gcc/ * cfgexpand.c (expand_asm_stmt): If errors are emitted, remove all inputs, outputs and clobbers from the asm and set template to "". gcc/c/ * c-typeck.c (c_mark_addressable): Diagnose trying to make bit-fields addressable. gcc/cp/ * typeck.c (cxx_mark_addressable): Diagnose trying to make bit-fields addressable. gcc/testsuite/ * c-c++-common/pr100785.c: New test. (cherry picked from commit 644c2cc5f2c09506a7bfef293a7f90efa8d7e5fa) Diff: --- gcc/c/c-typeck.c | 11 ++++++++- gcc/cfgexpand.c | 43 ++++++++++++++++++++++++++++------- gcc/cp/typeck.c | 7 +++++- gcc/testsuite/c-c++-common/pr100785.c | 21 +++++++++++++++++ 4 files changed, 72 insertions(+), 10 deletions(-) diff --git a/gcc/c/c-typeck.c b/gcc/c/c-typeck.c index d97363428d4..30330b298a8 100644 --- a/gcc/c/c-typeck.c +++ b/gcc/c/c-typeck.c @@ -4989,8 +4989,17 @@ c_mark_addressable (tree exp, bool array_ref_p) && TREE_CODE (TREE_TYPE (x)) == ARRAY_TYPE && VECTOR_TYPE_P (TREE_TYPE (TREE_OPERAND (x, 0)))) return true; - /* FALLTHRU */ + x = TREE_OPERAND (x, 0); + break; + case COMPONENT_REF: + if (DECL_C_BIT_FIELD (TREE_OPERAND (x, 1))) + { + error ("cannot take address of bit-field %qD", + TREE_OPERAND (x, 1)); + return false; + } + /* FALLTHRU */ case ADDR_EXPR: case ARRAY_REF: case REALPART_EXPR: diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index a7d05202184..9e0d4584704 100644 --- a/gcc/cfgexpand.c +++ b/gcc/cfgexpand.c @@ -2950,6 +2950,7 @@ expand_asm_stmt (gasm *stmt) unsigned ninputs = gimple_asm_ninputs (stmt); unsigned nlabels = gimple_asm_nlabels (stmt); unsigned i; + bool error_seen = false; /* ??? Diagnose during gimplification? */ if (ninputs + noutputs + nlabels > MAX_RECOG_OPERANDS) @@ -3008,6 +3009,7 @@ expand_asm_stmt (gasm *stmt) { /* ??? Diagnose during gimplification? */ error ("unknown register name %qs in %", regname); + error_seen = true; } else if (j == -4) { @@ -3071,7 +3073,10 @@ expand_asm_stmt (gasm *stmt) && REG_P (DECL_RTL (output_tvec[j])) && HARD_REGISTER_P (DECL_RTL (output_tvec[j])) && output_hregno == REGNO (DECL_RTL (output_tvec[j]))) - error ("invalid hard register usage between output operands"); + { + error ("invalid hard register usage between output operands"); + error_seen = true; + } /* Verify matching constraint operands use the same hard register and that the non-matching constraint operands do not use the same @@ -3094,13 +3099,19 @@ expand_asm_stmt (gasm *stmt) } if (i == match && output_hregno != input_hregno) - error ("invalid hard register usage between output operand " - "and matching constraint operand"); + { + error ("invalid hard register usage between output " + "operand and matching constraint operand"); + error_seen = true; + } else if (early_clobber_p && i != match && output_hregno == input_hregno) - error ("invalid hard register usage between earlyclobber " - "operand and input operand"); + { + error ("invalid hard register usage between " + "earlyclobber operand and input operand"); + error_seen = true; + } } } @@ -3178,7 +3189,10 @@ expand_asm_stmt (gasm *stmt) op = validize_mem (op); if (! allows_reg && !MEM_P (op)) - error ("output number %d not directly addressable", i); + { + error ("output number %d not directly addressable", i); + error_seen = true; + } if ((! allows_mem && MEM_P (op) && GET_MODE (op) != BLKmode) || GET_CODE (op) == CONCAT) { @@ -3218,6 +3232,19 @@ expand_asm_stmt (gasm *stmt) inout_opnum.safe_push (i); } + const char *str = gimple_asm_string (stmt); + if (error_seen) + { + ninputs = 0; + noutputs = 0; + inout_opnum.truncate (0); + output_rvec.truncate (0); + clobber_rvec.truncate (0); + constraints.truncate (0); + CLEAR_HARD_REG_SET (clobbered_regs); + str = ""; + } + auto_vec input_rvec; auto_vec input_mode; @@ -3275,7 +3302,7 @@ expand_asm_stmt (gasm *stmt) } /* For in-out operands, copy output rtx to input rtx. */ - unsigned ninout = inout_opnum.length(); + unsigned ninout = inout_opnum.length (); for (i = 0; i < ninout; i++) { int j = inout_opnum[i]; @@ -3329,7 +3356,7 @@ expand_asm_stmt (gasm *stmt) rtx body = gen_rtx_ASM_OPERANDS ((noutputs == 0 ? VOIDmode : GET_MODE (output_rvec[0])), - ggc_strdup (gimple_asm_string (stmt)), + ggc_strdup (str), "", 0, argvec, constraintvec, labelvec, locus); MEM_VOLATILE_P (body) = gimple_asm_volatile_p (stmt); diff --git a/gcc/cp/typeck.c b/gcc/cp/typeck.c index ab703a3ff07..4321ce5d04b 100644 --- a/gcc/cp/typeck.c +++ b/gcc/cp/typeck.c @@ -6665,9 +6665,14 @@ cxx_mark_addressable (tree exp, bool array_ref_p) && TREE_CODE (TREE_TYPE (x)) == ARRAY_TYPE && VECTOR_TYPE_P (TREE_TYPE (TREE_OPERAND (x, 0)))) return true; + x = TREE_OPERAND (x, 0); + break; + + case COMPONENT_REF: + if (bitfield_p (x)) + error ("attempt to take address of bit-field"); /* FALLTHRU */ case ADDR_EXPR: - case COMPONENT_REF: case ARRAY_REF: case REALPART_EXPR: case IMAGPART_EXPR: diff --git a/gcc/testsuite/c-c++-common/pr100785.c b/gcc/testsuite/c-c++-common/pr100785.c new file mode 100644 index 00000000000..1095845e6f1 --- /dev/null +++ b/gcc/testsuite/c-c++-common/pr100785.c @@ -0,0 +1,21 @@ +/* PR inline-asm/100785 */ + +struct S { int a : 1; }; + +void +foo (struct S *x) +{ + __asm__ ("" : "+m" (x->a)); /* { dg-error "address of bit-field" } */ +} /* { dg-error "invalid lvalue in asm output 0" "" { target c } .-1 } */ + /* { dg-error "memory input 1 is not directly addressable" "" { target c } .-2 } */ +void +bar (struct S *x) +{ + __asm__ ("" : "=m" (x->a)); /* { dg-error "address of bit-field" } */ +} /* { dg-error "invalid lvalue in asm output 0" "" { target c } .-1 } */ + +void +baz (struct S *x) +{ + __asm__ ("" : : "m" (x->a)); /* { dg-error "address of bit-field" } */ +} /* { dg-error "memory input 0 is not directly addressable" "" { target c } .-1 } */