[gcc r9-10126] i386: Fix up cvtsd2ss splitter [PR104502]

[Jakub Jelinek <jakub@gcc.gnu.org>]

https://gcc.gnu.org/g:cb412e0e881adcc5440ed37a8a415a77fe3df980

commit r9-10126-gcb412e0e881adcc5440ed37a8a415a77fe3df980
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Feb 12 11:17:41 2022 +0100

    i386: Fix up cvtsd2ss splitter [PR104502]
    
    The following testcase ICEs, because AVX512F is enabled, AVX512VL is not,
    and the cvtsd2ss insn has %xmm0-15 as output operand and %xmm16-31 as
    input operand.  For output operand %xmm16+ the splitter just gives up
    in such case, but for such input it just emits vmovddup which requires
    AVX512VL if either operand is EXT_REX_SSE_REG_P (when it is 128-bit).
    
    The following patch fixes it by treating that case like the pre-SSE3
    output != input case - move the input to output and do everything on
    the output reg which is known to be < %xmm16.
    
    2022-02-12  Jakub Jelinek  <jakub@redhat.com>
    
            PR target/104502
            * config/i386/i386.md (cvtsd2ss splitter): If operands[1] is xmm16+
            and AVX512VL isn't available, move operands[1] to operands[0] first.
    
            * gcc.target/i386/pr104502.c: New test.
    
    (cherry picked from commit 0538d42cdd68f6b65d72ed7768f1d00ba44f8631)

Diff:
---
 gcc/config/i386/i386.md                  |  4 ++--
 gcc/testsuite/gcc.target/i386/pr104502.c | 31 +++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 8144d7ba9c3..00a1db3ec0c 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -4613,8 +4613,8 @@
      movddup is available.  */
   if (REG_P (operands[1]))
     {
-      if (!TARGET_SSE3
-	  && REGNO (operands[0]) != REGNO (operands[1]))
+      if ((!TARGET_SSE3 && REGNO (operands[0]) != REGNO (operands[1]))
+	  || (EXT_REX_SSE_REG_P (operands[1]) && !TARGET_AVX512VL))
 	{
 	  rtx tmp = lowpart_subreg (DFmode, operands[0], SFmode);
 	  emit_move_insn (tmp, operands[1]);
diff --git a/gcc/testsuite/gcc.target/i386/pr104502.c b/gcc/testsuite/gcc.target/i386/pr104502.c
new file mode 100644
index 00000000000..7a6eb260e41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104502.c
@@ -0,0 +1,31 @@
+/* PR target/104502 */
+/* { dg-do compile { target fstack_protector } } */
+/* { dg-options "-O -flive-range-shrinkage -march=barcelona -fstack-protector-all -mavx512f" } */
+
+typedef char __attribute__((__vector_size__ (8))) U;
+typedef int __attribute__((__vector_size__ (8))) A;
+typedef int __attribute__((__vector_size__ (16))) B;
+typedef int __attribute__((__vector_size__ (32))) C;
+typedef int __attribute__((__vector_size__ (64))) D;
+typedef __float128 __attribute__((__vector_size__ (32))) F;
+
+char s;
+U u;
+A a;
+int i;
+C c;
+double d;
+
+U
+foo (U u0, A a0, B b0, B b1, C c0, C c1, C c2, C c3, A a1, A a2, F f0)
+{
+  C ca = c |= (short) (float) d;
+  C cb = c0 + c1 + c2 + c3 + ca + (C) f0;
+  U ua = s << (u & 4);
+  B ba = ((union {C a; B b;}) cb).b + b0 + b1;
+  U ub = ((union {B a; U b;}) ba).b +
+    u0 + u + ua + (U) a + (U) a + (U) a0 + (U) a1 + (U) a2;
+  long long u64_r = i + d;
+  char u8_r = u64_r;
+  return ub + u8_r;
+}