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From: Jakub Jelinek <jakub@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r9-10144] i386: Fix up ix86_expand_vector_init_general [PR105123] Date: Wed, 11 May 2022 06:26:10 +0000 (GMT) [thread overview] Message-ID: <20220511062610.3237838515F7@sourceware.org> (raw) https://gcc.gnu.org/g:a78199c69f794a4ccacd123adbe1aaa29b077fa1 commit r9-10144-ga78199c69f794a4ccacd123adbe1aaa29b077fa1 Author: Jakub Jelinek <jakub@redhat.com> Date: Sun Apr 3 21:50:43 2022 +0200 i386: Fix up ix86_expand_vector_init_general [PR105123] The following testcase is miscompiled on ia32. The problem is that at -O0 we end up with: vector(4) short unsigned int _1; short unsigned int u.0_3; ... _1 = {u.0_3, u.0_3, u.0_3, u.0_3}; statement (dead) which is wrongly expanded. elt is (subreg:HI (reg:SI 83 [ u.0_3 ]) 0), tmp_mode SImode, so after convert_mode we start with word (reg:SI 83 [ u.0_3 ]). The intent is to manually broadcast that value to 2 SImode parts, but because we pass word as target to expand_simple_binop, it will overwrite (reg:SI 83 [ u.0_3 ]) and we end up with 0: 10: {r83:SI=r83:SI<<0x10;clobber flags:CC;} 11: {r83:SI=r83:SI|r83:SI;clobber flags:CC;} 12: {r83:SI=r83:SI<<0x10;clobber flags:CC;} 13: {r83:SI=r83:SI|r83:SI;clobber flags:CC;} 14: clobber r110:V4HI 15: r110:V4HI#0=r83:SI 16: r110:V4HI#4=r83:SI as the two ors do nothing and two shifts each by 16 left shift it all away. The following patch fixes that by using NULL_RTX target, so we expand it as 10: {r110:SI=r83:SI<<0x10;clobber flags:CC;} 11: {r111:SI=r110:SI|r83:SI;clobber flags:CC;} 12: {r112:SI=r83:SI<<0x10;clobber flags:CC;} 13: {r113:SI=r112:SI|r83:SI;clobber flags:CC;} 14: clobber r114:V4HI 15: r114:V4HI#0=r111:SI 16: r114:V4HI#4=r113:SI instead. Another possibility would be to pass NULL_RTX only when word == elt and word otherwise, where word would necessarily be a pseudo from the first shift after passing NULL_RTX there once or pass NULL_RTX for the shift and word for ior. 2022-04-03 Jakub Jelinek <jakub@redhat.com> PR target/105123 * config/i386/i386.c (ix86_expand_vector_init_general): Avoid using word as target for expand_simple_binop when doing ASHIFT and IOR. * gcc.target/i386/pr105123.c: New test. (cherry picked from commit e1a74058b784c845e84a0cf1997b54b984df483d) Diff: --- gcc/config/i386/i386.c | 4 ++-- gcc/testsuite/gcc.target/i386/pr105123.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index cb631f7c829..502346ffea0 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -43376,9 +43376,9 @@ quarter: else { word = expand_simple_binop (word_mode, ASHIFT, word, shift, - word, 1, OPTAB_LIB_WIDEN); + NULL_RTX, 1, OPTAB_LIB_WIDEN); word = expand_simple_binop (word_mode, IOR, word, elt, - word, 1, OPTAB_LIB_WIDEN); + NULL_RTX, 1, OPTAB_LIB_WIDEN); } } diff --git a/gcc/testsuite/gcc.target/i386/pr105123.c b/gcc/testsuite/gcc.target/i386/pr105123.c new file mode 100644 index 00000000000..f00d98881a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105123.c @@ -0,0 +1,22 @@ +/* PR target/105123 */ +/* { dg-do run { target sse2_runtime } } */ +/* { dg-options "-msse2" } */ +/* { dg-additional-options "-mtune=i686" { target ia32 } } */ + +typedef unsigned short __attribute__((__vector_size__ (4 * sizeof (unsigned short)))) V; + +V +foo (unsigned short u, V v) +{ + return __builtin_shuffle (u * v, v); +} + +int +main () +{ + V x = foo (1, (V) { 0, 1, 2, 3 }); + for (unsigned i = 0; i < 4; i++) + if (x[i] != i) + __builtin_abort (); + return 0; +}
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