From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2063) id 217DA3850435; Wed, 11 May 2022 07:22:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 217DA3850435 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kewen Lin To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-283] rs6000: Fix constraint v with rs6000_constraints[RS6000_CONSTRAINT_v] X-Act-Checkin: gcc X-Git-Author: Kewen Lin X-Git-Refname: refs/heads/master X-Git-Oldrev: 9e1e962eac8d2a28fcd648a0f5c8eb0022abd8e4 X-Git-Newrev: 55aa130ef112c6f2c8ef85c218455464c6b29d60 Message-Id: <20220511072244.217DA3850435@sourceware.org> Date: Wed, 11 May 2022 07:22:44 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 May 2022 07:22:44 -0000 https://gcc.gnu.org/g:55aa130ef112c6f2c8ef85c218455464c6b29d60 commit r13-283-g55aa130ef112c6f2c8ef85c218455464c6b29d60 Author: Kewen Lin Date: Wed May 11 01:18:30 2022 -0500 rs6000: Fix constraint v with rs6000_constraints[RS6000_CONSTRAINT_v] Currently we hardcode ALTIVEC_REGS for register constraint v and RS6000_CONSTRAINT_v looks confusing, this is to fix it with rs6000_constraints[RS6000_CONSTRAINT_v] to align with some other existing register constraints with RS6000_CONSTRAINT_*. gcc/ChangeLog: * config/rs6000/constraints.md (register constraint v): Use rs6000_constraints[RS6000_CONSTRAINT_v] instead of ALTIVEC_REGS. Diff: --- gcc/config/rs6000/constraints.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 7aaffd9f9a8..b361893e289 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -37,7 +37,7 @@ historically @code{f} was for single-precision and @code{d} was for double-precision floating point.") -(define_register_constraint "v" "ALTIVEC_REGS" +(define_register_constraint "v" "rs6000_constraints[RS6000_CONSTRAINT_v]" "An Altivec vector register (VR), @code{v0}@dots{}@code{v31}.") (define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]"