From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 910AA3858427; Thu, 12 May 2022 22:47:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 910AA3858427 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work089)] Update ChangeLog.meissner. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work089 X-Git-Oldrev: 3346796d576bb7d3e3b2d2f542b80684131d6f87 X-Git-Newrev: 096bd8ff2b196415b4a61303ca474d7c7eb8e939 Message-Id: <20220512224716.910AA3858427@sourceware.org> Date: Thu, 12 May 2022 22:47:16 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 May 2022 22:47:16 -0000 https://gcc.gnu.org/g:096bd8ff2b196415b4a61303ca474d7c7eb8e939 commit 096bd8ff2b196415b4a61303ca474d7c7eb8e939 Author: Michael Meissner Date: Thu May 12 18:46:59 2022 -0400 Update ChangeLog.meissner. 2022-05-12 Michael Meissner gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 0e1adbcaee4..acc5d7be01c 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,72 @@ +==================== work089 patch #6 + +Optimize multiply/add of DImode extended to TImode, PR target/103109. + +On power9 and power10 systems, we have instructions that support doing +64-bit integers converted to 128-bit integers and producing 128-bit +results. This patch adds support to generate these instructions. + +Previously GCC had define_expands to handle conversion of the 64-bit +extend to 128-bit and multiply. This patch changes these define_expands +to define_insn_and_split and then it provides combiner patterns to +generate thes multiply/add instructions. + +To support using this optimization on power9, this patch extend the sign +extend DImode to TImode to also run on power9 (added for PR +target/104698). + +This patch needs the previous patch to add unsigned DImode to TImode +conversion so that the combiner can combine the extend, multiply, and add +instructions. + + +2022-05-12 Michael Meissner + +gcc/ + PR target/103109 + * config/rs6000/rs6000.md (su_int32): New code attribute. + (mul3): Convert from define_expand to + define_insn_and_split. + (maddld4): Add generator function. + (mulditi3_adddi3): New insn. + (mulditi3_add_const): New insn. + (mulditi3_adddi3_upper): New insn. + +gcc/testsuite/ + PR target/103109 + * gcc.target/powerpc/pr103109.c: New test. + +==================== work089 patch #5 + +Add zero_extendditi2. Improve lxvr*x code generation. + +This pattern adds zero_extendditi2 so that if we are extending DImode to +TImode, and we want the result in a vector register, the compiler can +generate MTVSRDDD. + +In addition the patterns for generating lxvr{b,h,w,d}x were tuned to allow +loading to gpr registers. This prevents needlessly doing direct moves to +get the value into the vector registers if the gpr register was already +selected. + +In updating the insn counts for two tests due to these changes, I noticed +the tests were done at -O0. I changed this so that the tests are now done +at the normal -O2 optimization level. + +2022-05-012 Michael Meissner + +gcc/ + * config/rs6000/vsx.md (vsx_lxvrx): Add support for loading to + GPR registers. + (vsx_stxvrx): Add support for storing from GPR registers. + (zero_extendditi2): New insn. + +gcc/testsuite/ + * gcc.target/powerpc/vsx-load-element-extend-int.c: Use -O2 + instead of -O0 and update insn counts. + * gcc.target/powerpc/vsx-load-element-extend-short.c: Likewise. + * gcc.target/powerpc/zero-extend-di-ti.c: New test. + ==================== work089 patch #4 Delay splitting addti3/subti3 until first split pass.