[gcc r13-415] xtensa: Reflect the 32-bit Integer Divide Option

[gcc r13-415] xtensa: Reflect the 32-bit Integer Divide Option

[Max Filippov]

https://gcc.gnu.org/g:112447f8564c0307c5da99a4094a3a99f204239f

commit r13-415-g112447f8564c0307c5da99a4094a3a99f204239f
Author: Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
Date:   Fri May 6 19:34:19 2022 +0900

    xtensa: Reflect the 32-bit Integer Divide Option
    
    On Espressif's ESP8266 (based on Tensilica LX106, no hardware divider),
    this patch reduces the size of each:
    
      __moddi3() @ libgcc.a :  969 -> 301 (saves 668)
      __divmoddi4()         : 1111 -> 426 (saves 685)
      __udivmoddi4()        : 1043 -> 319 (saves 724)
    
    in bytes, respectively.
    
    gcc/ChangeLog:
    
            * config/xtensa/xtensa.h (TARGET_HAS_NO_HW_DIVIDE): New macro
            definition.

Diff:
---
 gcc/config/xtensa/xtensa.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index 00e2930b30a..d25594f0c1f 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -75,6 +75,11 @@ along with GCC; see the file COPYING3.  If not see
 #define HAVE_AS_TLS 0
 #endif
 
+/* Define this if the target has no hardware divide instructions.  */
+#if !TARGET_DIV32
+#define TARGET_HAS_NO_HW_DIVIDE
+#endif
+
 \f
 /* Target CPU builtins.  */
 #define TARGET_CPU_CPP_BUILTINS()					\