From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1363) id DD0953858C51; Sun, 15 May 2022 20:08:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DD0953858C51 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" From: Uros Bizjak To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-466] i386: Remove constraints when used with constant integer predicates. X-Act-Checkin: gcc X-Git-Author: Uros Bizjak X-Git-Refname: refs/heads/master X-Git-Oldrev: 4df735e01e319997841574f353d2aa076a0335c2 X-Git-Newrev: 18547874ee205d830acb31f1e3c1c89fc7725c14 Message-Id: <20220515200825.DD0953858C51@sourceware.org> Date: Sun, 15 May 2022 20:08:25 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 May 2022 20:08:26 -0000 https://gcc.gnu.org/g:18547874ee205d830acb31f1e3c1c89fc7725c14 commit r13-466-g18547874ee205d830acb31f1e3c1c89fc7725c14 Author: Uros Bizjak Date: Sun May 15 22:07:46 2022 +0200 i386: Remove constraints when used with constant integer predicates. const_int_operand and other const*_operand predicates do not need constraints when the constraint is inherited from the range of constant integer predicate. Remove the constraint in case all alternatives use the same inherited constraint. 2022-05-15 Uroš Bizjak gcc/ChangeLog: * config/i386/i386.md: Remove constraints when used with const_int_operand, const0_operand, const_1_operand, constm1_operand, const8_operand, const128_operand, const248_operand, const123_operand, const2367_operand, const1248_operand, const359_operand, const_4_or_8_to_11_operand, const48_operand, const_0_to_1_operand, const_0_to_3_operand, const_0_to_4_operand, const_0_to_5_operand, const_0_to_7_operand, const_0_to_15_operand, const_0_to_31_operand, const_0_to_63_operand, const_0_to_127_operand, const_0_to_255_operand, const_0_to_255_mul_8_operand, const_1_to_31_operand, const_1_to_63_operand, const_2_to_3_operand, const_4_to_5_operand, const_4_to_7_operand, const_6_to_7_operand, const_8_to_9_operand, const_8_to_11_operand, const_8_to_15_operand, const_10_to_11_operand, const_12_to_13_operand, const_12_to_15_operand, const_14_to_15_operand, const_16_to_19_operand, const_16_to_31_operand, const_20_to_23_operand, const_24_to_27_operand and const_28_to_31_operand. * config/i386/mmx.md: Ditto. * config/i386/sse.md: Ditto. * config/i386/subst.md: Ditto. * config/i386/sync.md: Ditto. Diff: --- gcc/config/i386/i386.md | 98 ++++++------- gcc/config/i386/mmx.md | 20 +-- gcc/config/i386/sse.md | 366 +++++++++++++++++++++++------------------------ gcc/config/i386/subst.md | 10 +- gcc/config/i386/sync.md | 4 +- 5 files changed, 249 insertions(+), 249 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index f9c06ff302a..1d7ff256e62 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -6281,7 +6281,7 @@ [(set (reg FLAGS_REG) (compare (match_operand:SWI124 1 "nonimmediate_operand" "0") - (match_operand:SWI124 2 "const_int_operand" "n"))) + (match_operand:SWI124 2 "const_int_operand"))) (clobber (match_scratch:SWI124 0 "="))] "ix86_match_ccmode (insn, CCGCmode)" { @@ -6487,7 +6487,7 @@ (eq:CCO (plus: (sign_extend: (match_operand:SWI 1 "nonimmediate_operand" "0")) - (match_operand: 3 "const_int_operand" "i")) + (match_operand: 3 "const_int_operand")) (sign_extend: (plus:SWI (match_dup 1) @@ -6560,7 +6560,7 @@ (plus: (sign_extend: (match_operand: 1 "nonimmediate_operand" "%0")) - (match_operand: 3 "const_scalar_int_operand" "")) + (match_operand: 3 "const_scalar_int_operand")) (sign_extend: (plus: (match_dup 1) @@ -6645,7 +6645,7 @@ [(match_operand 3 "flags_reg_operand") (const_int 0)]) (sign_extend: (match_operand:SWI 1 "nonimmediate_operand" "%0"))) - (match_operand: 6 "const_int_operand" "")) + (match_operand: 6 "const_int_operand")) (sign_extend: (plus:SWI (plus:SWI @@ -6810,8 +6810,8 @@ (any_or:SWI12 (ashift:SWI12 (match_operand:SWI12 1 "index_register_operand" "l") - (match_operand 2 "const_0_to_3_operand" "n")) - (match_operand 3 "const_int_operand" "n")))] + (match_operand 2 "const_0_to_3_operand")) + (match_operand 3 "const_int_operand")))] "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)) && ((unsigned HOST_WIDE_INT) INTVAL (operands[3]) < (HOST_WIDE_INT_1U << INTVAL (operands[2])))" @@ -6834,8 +6834,8 @@ (any_or:SWI48 (ashift:SWI48 (match_operand:SWI48 1 "index_register_operand" "l") - (match_operand 2 "const_0_to_3_operand" "n")) - (match_operand 3 "const_int_operand" "n")))] + (match_operand 2 "const_0_to_3_operand")) + (match_operand 3 "const_int_operand")))] "(unsigned HOST_WIDE_INT) INTVAL (operands[3]) < (HOST_WIDE_INT_1U << INTVAL (operands[2]))" "#" @@ -7031,7 +7031,7 @@ (eq:CCO (minus: (sign_extend: (match_operand:SWI 1 "nonimmediate_operand" "0")) - (match_operand: 3 "const_int_operand" "i")) + (match_operand: 3 "const_int_operand")) (sign_extend: (minus:SWI (match_dup 1) @@ -7099,7 +7099,7 @@ (minus: (sign_extend: (match_operand: 1 "nonimmediate_operand" "0")) - (match_operand: 3 "const_scalar_int_operand" "")) + (match_operand: 3 "const_scalar_int_operand")) (sign_extend: (minus: (match_dup 1) @@ -7182,7 +7182,7 @@ (match_operand:SWI 1 "nonimmediate_operand" "%0")) (match_operator: 4 "ix86_carry_flag_operator" [(match_operand 3 "flags_reg_operand") (const_int 0)])) - (match_operand: 6 "const_int_operand" "")) + (match_operand: 6 "const_int_operand")) (sign_extend: (minus:SWI (minus:SWI @@ -7452,7 +7452,7 @@ (match_operand:SWI48 1 "nonimmediate_operand" "%0")) (match_operand:SWI48 2 "x86_64_immediate_operand" "e"))) (plus: - (match_operand: 6 "const_scalar_int_operand" "") + (match_operand: 6 "const_scalar_int_operand") (match_operator: 4 "ix86_carry_flag_operator" [(match_dup 3) (const_int 0)])))) (set (match_operand:SWI48 0 "nonimmediate_operand" "=rm") @@ -8446,7 +8446,7 @@ (lshiftrt: (mult: (zero_extend: (match_dup 2)) (zero_extend: (match_dup 3))) - (match_operand:QI 4 "const_int_operand" "n"))))] + (match_operand:QI 4 "const_int_operand"))))] "TARGET_BMI2 && INTVAL (operands[4]) == * BITS_PER_UNIT && !(MEM_P (operands[1]) && MEM_P (operands[2]))" "mulx\t{%3, %0, %1|%1, %0, %3}" @@ -9080,7 +9080,7 @@ (define_insn_and_split "*udivmod4_pow2" [(set (match_operand:SWI48 0 "register_operand" "=r") (udiv:SWI48 (match_operand:SWI48 2 "register_operand" "0") - (match_operand:SWI48 3 "const_int_operand" "n"))) + (match_operand:SWI48 3 "const_int_operand"))) (set (match_operand:SWI48 1 "register_operand" "=r") (umod:SWI48 (match_dup 2) (match_dup 3))) (clobber (reg:CC FLAGS_REG))] @@ -9161,7 +9161,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (udiv:SI (match_operand:SI 2 "register_operand" "0") - (match_operand:SI 3 "const_int_operand" "n")))) + (match_operand:SI 3 "const_int_operand")))) (set (match_operand:SI 1 "register_operand" "=r") (umod:SI (match_dup 2) (match_dup 3))) (clobber (reg:CC FLAGS_REG))] @@ -9245,7 +9245,7 @@ [(set (match_operand:DI 1 "register_operand" "=r") (zero_extend:DI (umod:SI (match_operand:SI 2 "register_operand" "0") - (match_operand:SI 3 "const_int_operand" "n")))) + (match_operand:SI 3 "const_int_operand")))) (set (match_operand:SI 0 "register_operand" "=r") (udiv:SI (match_dup 2) (match_dup 3))) (clobber (reg:CC FLAGS_REG))] @@ -9312,7 +9312,7 @@ ;; Avoid sign-extension (using cdq) for constant numerators. (define_insn_and_split "*divmodsi4_const" [(set (match_operand:SI 0 "register_operand" "=&a") - (div:SI (match_operand:SI 2 "const_int_operand" "n") + (div:SI (match_operand:SI 2 "const_int_operand") (match_operand:SI 3 "nonimmediate_operand" "rm"))) (set (match_operand:SI 1 "register_operand" "=&d") (mod:SI (match_dup 2) (match_dup 3))) @@ -9597,8 +9597,8 @@ (match_operator 1 "compare_operator" [(zero_extract:SWI248 (match_operand 2 "int_nonimmediate_operand" "rm") - (match_operand 3 "const_int_operand" "n") - (match_operand 4 "const_int_operand" "n")) + (match_operand 3 "const_int_operand") + (match_operand 4 "const_int_operand")) (const_int 0)]))] "/* Ensure that resulting mask is zero or sign extended operand. */ INTVAL (operands[4]) >= 0 @@ -9851,7 +9851,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0") - (match_operand:DI 2 "const_int_operand" "n"))) + (match_operand:DI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_USE_BT && ix86_binary_operator_ok (AND, DImode, operands) @@ -10481,7 +10481,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0") - (match_operand:DI 2 "const_int_operand" "n"))) + (match_operand:DI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_USE_BT && ix86_binary_operator_ok (IOR, DImode, operands) @@ -10503,7 +10503,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0") - (match_operand:DI 2 "const_int_operand" "n"))) + (match_operand:DI 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && TARGET_USE_BT && ix86_binary_operator_ok (XOR, DImode, operands) @@ -11860,12 +11860,12 @@ (define_insn "*x86_64_shld_1" [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m") (ior:DI (ashift:DI (match_dup 0) - (match_operand:QI 2 "const_0_to_63_operand" "J")) + (match_operand:QI 2 "const_0_to_63_operand")) (subreg:DI (lshiftrt:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) - (match_operand:QI 3 "const_0_to_255_operand" "N")) 0))) + (match_operand:QI 3 "const_0_to_255_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && INTVAL (operands[3]) == 64 - INTVAL (operands[2])" @@ -11924,12 +11924,12 @@ (define_insn "*x86_shld_1" [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m") (ior:SI (ashift:SI (match_dup 0) - (match_operand:QI 2 "const_0_to_31_operand" "I")) + (match_operand:QI 2 "const_0_to_31_operand")) (subreg:SI (lshiftrt:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:QI 3 "const_0_to_63_operand" "J")) 0))) + (match_operand:QI 3 "const_0_to_63_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "INTVAL (operands[3]) == 32 - INTVAL (operands[2])" "shld{l}\t{%2, %1, %0|%0, %1, %2}" @@ -12449,7 +12449,7 @@ [(set (reg FLAGS_REG) (compare (ashift:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:QI 2 "const_1_to_31_operand" "I")) + (match_operand:QI 2 "const_1_to_31_operand")) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))] @@ -12783,12 +12783,12 @@ (define_insn "*x86_64_shrd_1" [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m") (ior:DI (lshiftrt:DI (match_dup 0) - (match_operand:QI 2 "const_0_to_63_operand" "J")) + (match_operand:QI 2 "const_0_to_63_operand")) (subreg:DI (ashift:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) - (match_operand:QI 3 "const_0_to_255_operand" "N")) 0))) + (match_operand:QI 3 "const_0_to_255_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && INTVAL (operands[3]) == 64 - INTVAL (operands[2])" @@ -12847,12 +12847,12 @@ (define_insn "*x86_shrd_1" [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m") (ior:SI (lshiftrt:SI (match_dup 0) - (match_operand:QI 2 "const_0_to_31_operand" "I")) + (match_operand:QI 2 "const_0_to_31_operand")) (subreg:SI (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r")) - (match_operand:QI 3 "const_0_to_63_operand" "J")) 0))) + (match_operand:QI 3 "const_0_to_63_operand")) 0))) (clobber (reg:CC FLAGS_REG))] "INTVAL (operands[3]) == 32 - INTVAL (operands[2])" "shrd{l}\t{%2, %1, %0|%0, %1, %2}" @@ -13260,7 +13260,7 @@ [(set (reg FLAGS_REG) (compare (any_shiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:QI 2 "const_1_to_31_operand" "I")) + (match_operand:QI 2 "const_1_to_31_operand")) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))] @@ -13637,7 +13637,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "rm") - (match_operand:QI 2 "const_0_to_31_operand" "I"))))] + (match_operand:QI 2 "const_0_to_31_operand"))))] "TARGET_64BIT && TARGET_BMI2 && !optimize_function_for_size_p (cfun)" "rorx\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "rotatex") @@ -13990,7 +13990,7 @@ (define_insn "*btsq_imm" [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm") (const_int 1) - (match_operand 1 "const_0_to_63_operand" "J")) + (match_operand 1 "const_0_to_63_operand")) (const_int 1)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -14003,7 +14003,7 @@ (define_insn "*btrq_imm" [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm") (const_int 1) - (match_operand 1 "const_0_to_63_operand" "J")) + (match_operand 1 "const_0_to_63_operand")) (const_int 0)) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -14016,7 +14016,7 @@ (define_insn "*btcq_imm" [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm") (const_int 1) - (match_operand 1 "const_0_to_63_operand" "J")) + (match_operand 1 "const_0_to_63_operand")) (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1)))) (clobber (reg:CC FLAGS_REG))] "TARGET_64BIT && (TARGET_USE_BT || reload_completed)" @@ -14544,7 +14544,7 @@ (unspec:QI [(match_operand:HF 1 "register_operand" "v") (match_operand:HF 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_31_operand" "n")] + (match_operand:SI 3 "const_0_to_31_operand")] UNSPEC_PCMP))] "TARGET_AVX512FP16" "vcmpsh\t{%3, %2, %1, %0|%0, %1, %2, %3}" @@ -16561,7 +16561,7 @@ (zero_extract:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") (umin:SWI48 (and:SWI48 (match_dup 2) (const_int 255)) - (match_operand:SWI48 3 "const_int_operand" "n")) + (match_operand:SWI48 3 "const_int_operand")) (const_int 0)) (const_int 0))) (clobber (reg:CC FLAGS_REG))] @@ -16578,7 +16578,7 @@ (zero_extract:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") (umin:SWI48 (zero_extend:SWI48 (match_dup 2)) - (match_operand:SWI48 3 "const_int_operand" "n")) + (match_operand:SWI48 3 "const_int_operand")) (const_int 0)) (const_int 0))) (clobber (reg:CC FLAGS_REG))] @@ -16596,7 +16596,7 @@ (zero_extract:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") (umin:SWI48 (zero_extend:SWI48 (match_dup 2)) - (match_operand:SWI48 3 "const_int_operand" "n")) + (match_operand:SWI48 3 "const_int_operand")) (const_int 0)) (const_int 0)) (const_int 0))) @@ -16663,8 +16663,8 @@ [(set (match_operand:SWI48 0 "register_operand" "=r") (zero_extract:SWI48 (match_operand:SWI48 1 "nonimmediate_operand" "rm") - (match_operand 2 "const_0_to_255_operand" "N") - (match_operand 3 "const_0_to_255_operand" "N"))) + (match_operand 2 "const_0_to_255_operand") + (match_operand 3 "const_0_to_255_operand"))) (clobber (reg:CC FLAGS_REG))] "TARGET_TBM" { @@ -19287,7 +19287,7 @@ [(set (match_operand:MODEFH 0 "register_operand" "=x,x,x,v,v") (unspec:MODEFH [(match_operand:MODEFH 1 "nonimmediate_operand" "0,x,m,v,m") - (match_operand:SI 2 "const_0_to_15_operand" "n,n,n,n,n")] + (match_operand:SI 2 "const_0_to_15_operand")] UNSPEC_ROUND))] "TARGET_SSE4_1" "@ @@ -21479,7 +21479,7 @@ (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")] UNSPECV_PROBE_STACK_RANGE)) (set (reg:P SP_REG) - (minus:P (reg:P SP_REG) (match_operand:P 2 "const_int_operand" "n"))) + (minus:P (reg:P SP_REG) (match_operand:P 2 "const_int_operand"))) (clobber (reg:CC FLAGS_REG)) (clobber (mem:BLK (scratch)))] "" @@ -21489,7 +21489,7 @@ (define_insn "@probe_stack_range_" [(set (match_operand:P 0 "register_operand" "=r") (unspec_volatile:P [(match_operand:P 1 "register_operand" "0") - (match_operand:P 2 "const_int_operand" "n")] + (match_operand:P 2 "const_int_operand")] UNSPECV_PROBE_STACK_RANGE)) (clobber (reg:CC FLAGS_REG))] "" @@ -22933,7 +22933,7 @@ (define_insn "*prefetch_3dnow" [(prefetch (match_operand 0 "address_operand" "p") - (match_operand:SI 1 "const_int_operand" "n") + (match_operand:SI 1 "const_int_operand") (const_int 3))] "TARGET_3DNOW || TARGET_PRFCHW || TARGET_PREFETCHWT1" { @@ -23483,7 +23483,7 @@ (define_insn "@lwp_lwpval" [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r") (match_operand:SI 1 "nonimmediate_operand" "rm") - (match_operand:SI 2 "const_int_operand" "i")] + (match_operand:SI 2 "const_int_operand")] UNSPECV_LWPVAL_INTRINSIC)] "TARGET_LWP" "lwpval\t{%2, %1, %0|%0, %1, %2}" @@ -23496,7 +23496,7 @@ [(set (reg:CCC FLAGS_REG) (unspec_volatile:CCC [(match_operand:SWI48 0 "register_operand" "r") (match_operand:SI 1 "nonimmediate_operand" "rm") - (match_operand:SI 2 "const_int_operand" "i")] + (match_operand:SI 2 "const_int_operand")] UNSPECV_LWPINS_INTRINSIC))] "TARGET_LWP" "lwpins\t{%2, %1, %0|%0, %1, %2}" @@ -23702,7 +23702,7 @@ (set_attr "length" "3")]) (define_insn "xabort" - [(unspec_volatile [(match_operand:SI 0 "const_0_to_255_operand" "n")] + [(unspec_volatile [(match_operand:SI 0 "const_0_to_255_operand")] UNSPECV_XABORT)] "TARGET_RTM" "xabort\t%0" diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 197f19e4b1a..03aa01f8693 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -3454,7 +3454,7 @@ [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,m") (vec_select:HI (match_operand:V4HI 1 "register_operand" "y,YW,YW") - (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n")])))] + (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A)" "@ @@ -3473,7 +3473,7 @@ (zero_extend:SWI48 (vec_select:HI (match_operand:V4HI 1 "register_operand" "y,YW") - (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))] + (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A)" "@ @@ -3490,7 +3490,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m") (vec_select:QI (match_operand:V8QI 1 "register_operand" "YW,YW") - (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n,n")])))] + (parallel [(match_operand:SI 2 "const_0_to_7_operand")])))] "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE" "@ %vpextrb\t{%2, %1, %k0|%k0, %1, %2} @@ -3507,7 +3507,7 @@ (zero_extend:SWI248 (vec_select:QI (match_operand:V8QI 1 "register_operand" "YW") - (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))] + (parallel [(match_operand:SI 2 "const_0_to_7_operand")]))))] "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE" "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "sselog1") @@ -3630,7 +3630,7 @@ (vec_merge:V4HI (match_operand:V4HI 2 "register_operand" "Yr,*x,x") (match_operand:V4HI 1 "register_operand" "0,0,x") - (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")))] + (match_operand:SI 3 "const_0_to_15_operand")))] "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE" "@ pblendw\t{%3, %2, %0|%0, %2, %3} @@ -3648,7 +3648,7 @@ (vec_merge:V2HI (match_operand:V2HI 2 "register_operand" "Yr,*x,x") (match_operand:V2HI 1 "register_operand" "0,0,x") - (match_operand:SI 3 "const_0_to_7_operand" "n,n,n")))] + (match_operand:SI 3 "const_0_to_7_operand")))] "TARGET_SSE4_1" "@ pblendw\t{%3, %2, %0|%0, %2, %3} @@ -4035,7 +4035,7 @@ [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,m") (vec_select:HI (match_operand:V2HI 1 "register_operand" "YW,YW") - (parallel [(match_operand:SI 2 "const_0_to_1_operand" "n,n")])))] + (parallel [(match_operand:SI 2 "const_0_to_1_operand")])))] "TARGET_SSE2" "@ %vpextrw\t{%2, %1, %k0|%k0, %1, %2} @@ -4051,7 +4051,7 @@ (zero_extend:SWI48 (vec_select:HI (match_operand:V2HI 1 "register_operand" "YW") - (parallel [(match_operand:SI 2 "const_0_to_1_operand" "n")]))))] + (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))] "TARGET_SSE2" "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "sselog1") @@ -4063,7 +4063,7 @@ [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m") (vec_select:QI (match_operand:V4QI 1 "register_operand" "YW,YW") - (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")])))] + (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))] "TARGET_SSE4_1" "@ %vpextrb\t{%2, %1, %k0|%k0, %1, %2} @@ -4080,7 +4080,7 @@ (zero_extend:SWI248 (vec_select:QI (match_operand:V4QI 1 "register_operand" "YW") - (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))] + (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))] "TARGET_SSE4_1" "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "type" "sselog1") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 88fc5216a58..175ce013e5d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1484,7 +1484,7 @@ (match_operand:MODEFH 1 "memory_operand" "m")) (match_operand: 2 "nonimm_or_0_operand" "0C") (match_operand:QI 3 "register_operand" "Yk")) - (match_operand: 4 "const0_operand" "C") + (match_operand: 4 "const0_operand") (const_int 1)))] "TARGET_AVX512F" "vmov\t{%1, %0%{%3%}%N2|%0%{3%}%N2, %1}" @@ -1624,7 +1624,7 @@ (vec_select: (match_operand:VI8F_128 1 "nonimmediate_operand" "vm") (parallel [(const_int 0)])) - (match_operand: 2 "const0_operand" "C")))] + (match_operand: 2 "const0_operand")))] "TARGET_SSE2" "%vmovq\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") @@ -2018,7 +2018,7 @@ [(set (match_operand:SWI1248_AVX512BWDQ 0 "register_operand" "=k") (any_lshift:SWI1248_AVX512BWDQ (match_operand:SWI1248_AVX512BWDQ 1 "register_operand" "k") - (match_operand 2 "const_0_to_255_operand" "n"))) + (match_operand 2 "const_0_to_255_operand"))) (unspec [(const_int 0)] UNSPEC_MASKOP)] "TARGET_AVX512F" "k\t{%2, %1, %0|%0, %1, %2}" @@ -3440,7 +3440,7 @@ (unspec:VF_128_256 [(match_operand:VF_128_256 1 "register_operand" "x") (match_operand:VF_128_256 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_0_to_31_operand" "n")] + (match_operand:SI 3 "const_0_to_31_operand")] UNSPEC_PCMP))] "TARGET_AVX" "vcmp\t{%3, %2, %1, %0|%0, %1, %2, %3}" @@ -3652,7 +3652,7 @@ (unspec:VF_128 [(match_operand:VF_128 1 "register_operand" "x") (match_operand:VF_128 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_0_to_31_operand" "n")] + (match_operand:SI 3 "const_0_to_31_operand")] UNSPEC_PCMP) (match_dup 1) (const_int 1)))] @@ -3745,7 +3745,7 @@ (unspec: [(match_operand:V48H_AVX512VL 1 "nonimmediate_operand") (match_operand:V48H_AVX512VL 2 "nonimmediate_operand") - (match_operand:SI 3 "const_0_to_7_operand" "n")] + (match_operand:SI 3 "const_0_to_7_operand")] UNSPEC_PCMP)))] "TARGET_AVX512F && (!VALID_MASK_AVX512BW_MODE (mode) || TARGET_AVX512BW) @@ -3951,7 +3951,7 @@ (unspec: [(match_operand:VI12_AVX512VL 1 "register_operand" "v") (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_7_operand" "n")] + (match_operand:SI 3 "const_0_to_7_operand")] UNSPEC_UNSIGNED_PCMP))] "TARGET_AVX512BW" "vpcmpu\t{%3, %2, %1, %0|%0, %1, %2, %3}" @@ -4049,7 +4049,7 @@ (unspec: [(match_operand:VI48_AVX512VL 1 "register_operand" "v") (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_7_operand" "n")] + (match_operand:SI 3 "const_0_to_7_operand")] UNSPEC_UNSIGNED_PCMP))] "TARGET_AVX512F" "vpcmpu\t{%3, %2, %1, %0|%0, %1, %2, %3}" @@ -4189,7 +4189,7 @@ (unspec: [(match_operand:VFH_128 1 "register_operand" "v") (match_operand:VFH_128 2 "" "") - (match_operand:SI 3 "const_0_to_31_operand" "n")] + (match_operand:SI 3 "const_0_to_31_operand")] UNSPEC_PCMP) (const_int 1)))] "TARGET_AVX512F" @@ -4205,7 +4205,7 @@ (unspec: [(match_operand:VFH_128 1 "register_operand" "v") (match_operand:VFH_128 2 "" "") - (match_operand:SI 3 "const_0_to_31_operand" "n")] + (match_operand:SI 3 "const_0_to_31_operand")] UNSPEC_PCMP) (and: (match_operand: 4 "register_operand" "Yk") @@ -6075,7 +6075,7 @@ (match_operand:VFH_128 1 "register_operand" "0,0") (match_operand:VFH_128 2 "" ",v") (match_operand:VFH_128 3 "" "v,")) - (match_operand:VFH_128 4 "const0_operand" "C,C") + (match_operand:VFH_128 4 "const0_operand") (match_operand:QI 5 "register_operand" "Yk,Yk")) (match_dup 1) (const_int 1)))] @@ -6133,7 +6133,7 @@ (match_operand:VFH_128 2 "" ",v") (neg:VFH_128 (match_operand:VFH_128 3 "" "v,"))) - (match_operand:VFH_128 4 "const0_operand" "C,C") + (match_operand:VFH_128 4 "const0_operand") (match_operand:QI 5 "register_operand" "Yk,Yk")) (match_dup 1) (const_int 1)))] @@ -6205,7 +6205,7 @@ (match_operand:VFH_128 2 "" ",v")) (match_operand:VFH_128 1 "register_operand" "0,0") (match_operand:VFH_128 3 "" "v,")) - (match_operand:VFH_128 4 "const0_operand" "C,C") + (match_operand:VFH_128 4 "const0_operand") (match_operand:QI 5 "register_operand" "Yk,Yk")) (match_dup 1) (const_int 1)))] @@ -6266,7 +6266,7 @@ (match_operand:VFH_128 1 "register_operand" "0,0") (neg:VFH_128 (match_operand:VFH_128 3 "" "v,"))) - (match_operand:VFH_128 4 "const0_operand" "C,C") + (match_operand:VFH_128 4 "const0_operand") (match_operand:QI 5 "register_operand" "Yk,Yk")) (match_dup 1) (const_int 1)))] @@ -6931,7 +6931,7 @@ [(set (match_operand:V8HF 0 "register_operand" "=v") (vec_concat:V8HF (any_float:V4HF (match_operand:VI4_128_8_256 1 "vector_operand" "vm")) - (match_operand:V4HF 2 "const0_operand" "C")))] + (match_operand:V4HF 2 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvt2ph\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") @@ -6960,7 +6960,7 @@ (match_operand:V8HF 2 "nonimm_or_0_operand" "0C") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])) (match_operand:QI 3 "register_operand" "Yk")) - (match_operand:V4HF 4 "const0_operand" "C")))] + (match_operand:V4HF 4 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvt2ph\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" [(set_attr "type" "ssecvt") @@ -6973,9 +6973,9 @@ (vec_merge:V4HF (any_float:V4HF (match_operand:VI4_128_8_256 1 "vector_operand" "vm")) - (match_operand:V4HF 3 "const0_operand" "C") + (match_operand:V4HF 3 "const0_operand") (match_operand:QI 2 "register_operand" "Yk")) - (match_operand:V4HF 4 "const0_operand" "C")))] + (match_operand:V4HF 4 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvt2ph\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}" [(set_attr "type" "ssecvt") @@ -7007,7 +7007,7 @@ [(set (match_operand:V8HF 0 "register_operand" "=v") (vec_concat:V8HF (any_float:V2HF (match_operand:V2DI 1 "vector_operand" "vm")) - (match_operand:V6HF 2 "const0_operand" "C")))] + (match_operand:V6HF 2 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvtqq2ph{x}\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") @@ -7036,7 +7036,7 @@ (match_operand:V8HF 2 "nonimm_or_0_operand" "0C") (parallel [(const_int 0) (const_int 1)])) (match_operand:QI 3 "register_operand" "Yk")) - (match_operand:V6HF 4 "const0_operand" "C")))] + (match_operand:V6HF 4 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvtqq2ph{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" [(set_attr "type" "ssecvt") @@ -7049,9 +7049,9 @@ (vec_merge:V2HF (any_float:V2HF (match_operand:V2DI 1 "vector_operand" "vm")) - (match_operand:V2HF 3 "const0_operand" "C") + (match_operand:V2HF 3 "const0_operand") (match_operand:QI 2 "register_operand" "Yk")) - (match_operand:V6HF 4 "const0_operand" "C")))] + (match_operand:V6HF 4 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvtqq2ph{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}" [(set_attr "type" "ssecvt") @@ -7354,7 +7354,7 @@ (vec_concat:V8HF (float_truncate:V4HF (match_operand:VF4_128_8_256 1 "vector_operand" "vm")) - (match_operand:V4HF 2 "const0_operand" "C")))] + (match_operand:V4HF 2 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvt2ph\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") @@ -7387,7 +7387,7 @@ (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])) (match_operand:QI 3 "register_operand" "Yk")) - (match_operand:V4HF 4 "const0_operand" "C")))] + (match_operand:V4HF 4 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvt2ph\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" [(set_attr "type" "ssecvt") @@ -7400,9 +7400,9 @@ (vec_merge:V4HF (float_truncate:V4HF (match_operand:VF4_128_8_256 1 "vector_operand" "vm")) - (match_operand:V4HF 3 "const0_operand" "C") + (match_operand:V4HF 3 "const0_operand") (match_operand:QI 2 "register_operand" "Yk")) - (match_operand:V4HF 4 "const0_operand" "C")))] + (match_operand:V4HF 4 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvt2ph\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}" [(set_attr "type" "ssecvt") @@ -7433,7 +7433,7 @@ (vec_concat:V8HF (float_truncate:V2HF (match_operand:V2DF 1 "vector_operand" "vm")) - (match_operand:V6HF 2 "const0_operand" "C")))] + (match_operand:V6HF 2 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvtpd2ph{x}\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") @@ -7463,7 +7463,7 @@ (match_operand:V8HF 2 "nonimm_or_0_operand" "0C") (parallel [(const_int 0) (const_int 1)])) (match_operand:QI 3 "register_operand" "Yk")) - (match_operand:V6HF 4 "const0_operand" "C")))] + (match_operand:V6HF 4 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvtpd2ph{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" [(set_attr "type" "ssecvt") @@ -7476,9 +7476,9 @@ (vec_merge:V2HF (float_truncate:V2HF (match_operand:V2DF 1 "vector_operand" "vm")) - (match_operand:V2HF 3 "const0_operand" "C") + (match_operand:V2HF 3 "const0_operand") (match_operand:QI 2 "register_operand" "Yk")) - (match_operand:V6HF 4 "const0_operand" "C")))] + (match_operand:V6HF 4 "const0_operand")))] "TARGET_AVX512FP16 && TARGET_AVX512VL" "vcvtpd2ph{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}" [(set_attr "type" "ssecvt") @@ -8262,7 +8262,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_concat:V4SF (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm")) - (match_operand:V2SF 2 "const0_operand" "C")))] + (match_operand:V2SF 2 "const0_operand")))] "TARGET_AVX512DQ && TARGET_AVX512VL" "vcvtqq2ps{x}\t{%1, %0|%0, %1}" [(set_attr "type" "ssecvt") @@ -8337,7 +8337,7 @@ (match_operand:V4SF 2 "nonimm_or_0_operand" "0C") (parallel [(const_int 0) (const_int 1)])) (match_operand:QI 3 "register_operand" "Yk")) - (match_operand:V2SF 4 "const0_operand" "C")))] + (match_operand:V2SF 4 "const0_operand")))] "TARGET_AVX512DQ && TARGET_AVX512VL" "vcvtqq2ps{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" [(set_attr "type" "ssecvt") @@ -8350,9 +8350,9 @@ (vec_merge:V2SF (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm")) - (match_operand:V2SF 3 "const0_operand" "C") + (match_operand:V2SF 3 "const0_operand") (match_operand:QI 2 "register_operand" "Yk")) - (match_operand:V2SF 4 "const0_operand" "C")))] + (match_operand:V2SF 4 "const0_operand")))] "TARGET_AVX512DQ && TARGET_AVX512VL" "vcvtqq2ps{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}" [(set_attr "type" "ssecvt") @@ -8976,7 +8976,7 @@ (vec_concat:V4SF (float_truncate:V2SF (match_operand:V2DF 1 "vector_operand" "vBm")) - (match_operand:V2SF 2 "const0_operand" "C")))] + (match_operand:V2SF 2 "const0_operand")))] "TARGET_SSE2" { if (TARGET_AVX) @@ -9021,7 +9021,7 @@ (match_operand:V4SF 2 "nonimm_or_0_operand" "0C") (parallel [(const_int 0) (const_int 1)])) (match_operand:QI 3 "register_operand" "Yk")) - (match_operand:V2SF 4 "const0_operand" "C")))] + (match_operand:V2SF 4 "const0_operand")))] "TARGET_AVX512VL" "vcvtpd2ps{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}" [(set_attr "type" "ssecvt") @@ -9034,9 +9034,9 @@ (vec_merge:V2SF (float_truncate:V2SF (match_operand:V2DF 1 "nonimmediate_operand" "vm")) - (match_operand:V2SF 3 "const0_operand" "C") + (match_operand:V2SF 3 "const0_operand") (match_operand:QI 2 "register_operand" "Yk")) - (match_operand:V2SF 4 "const0_operand" "C")))] + (match_operand:V2SF 4 "const0_operand")))] "TARGET_AVX512VL" "vcvtpd2ps{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}" [(set_attr "type" "ssecvt") @@ -10571,7 +10571,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_concat:V4SF (match_operand:V2SF 1 "nonimmediate_operand" "vm") - (match_operand:V2SF 2 "const0_operand" " C")))] + (match_operand:V2SF 2 "const0_operand")))] "TARGET_SSE2" "%vmovq\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") @@ -10729,7 +10729,7 @@ (vec_merge:VI2F_256_512 (vec_duplicate:VI2F_256_512 (match_operand: 2 "nonimmediate_operand" "r,m")) - (match_operand:VI2F_256_512 1 "const0_operand" "C,C") + (match_operand:VI2F_256_512 1 "const0_operand") (const_int 1)))] "TARGET_AVX512FP16" "@ @@ -10829,7 +10829,7 @@ (vec_merge:VI4F_256_512 (vec_duplicate:VI4F_256_512 (match_operand: 2 "nonimmediate_operand" "v,m,r")) - (match_operand:VI4F_256_512 1 "const0_operand" "C,C,C") + (match_operand:VI4F_256_512 1 "const0_operand") (const_int 1)))] "TARGET_AVX" "@ @@ -10892,7 +10892,7 @@ [(set (match_operand:V4SF 0 "register_operand" "=Yr,*x,v") (unspec:V4SF [(match_operand:V4SF 2 "nonimmediate_operand" "Yrm,*xm,vm") (match_operand:V4SF 1 "register_operand" "0,0,v") - (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_INSERTPS))] "TARGET_SSE4_1" { @@ -11009,7 +11009,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,rm,Yv,Yv") (vec_select:SF (match_operand:V4SF 1 "register_operand" "Yr,*x,v,0,v") - (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n,n,n")])))] + (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))] "TARGET_SSE4_1" "@ extractps\t{%2, %1, %0|%0, %1, %2} @@ -11051,7 +11051,7 @@ [(set (match_operand:SF 0 "register_operand" "=v,*r,f") (vec_select:SF (match_operand:V4SF 1 "memory_operand" "o,o,o") - (parallel [(match_operand 2 "const_0_to_3_operand" "n,n,n")])))] + (parallel [(match_operand 2 "const_0_to_3_operand")])))] "TARGET_SSE" "#" "&& reload_completed" @@ -13534,7 +13534,7 @@ (vec_merge:VF2_512_256 (vec_duplicate:VF2_512_256 (match_operand: 2 "nonimmediate_operand" "vm")) - (match_operand:VF2_512_256 1 "const0_operand" "C") + (match_operand:VF2_512_256 1 "const0_operand") (const_int 1)))] "TARGET_AVX" "vmovq\t{%2, %x0|%x0, %2}" @@ -16021,7 +16021,7 @@ [(set (match_operand:VIMAX_AVX512VL 0 "register_operand" "=v") (any_lshift:VIMAX_AVX512VL (match_operand:VIMAX_AVX512VL 1 "nonimmediate_operand" "vm") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))] + (match_operand:SI 2 "const_0_to_255_mul_8_operand")))] "TARGET_AVX512BW" { operands[2] = GEN_INT (INTVAL (operands[2]) / 8); @@ -16036,7 +16036,7 @@ [(set (match_operand:VIMAX_AVX2 0 "register_operand" "=x,Yw") (any_lshift:VIMAX_AVX2 (match_operand:VIMAX_AVX2 1 "register_operand" "0,Yw") - (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n,n")))] + (match_operand:SI 2 "const_0_to_255_mul_8_operand")))] "TARGET_SSE2" { operands[2] = GEN_INT (INTVAL (operands[2]) / 8); @@ -18095,7 +18095,7 @@ (match_operand:AVX512_VEC 1 "reg_or_0_operand" "v,C,C") (vec_duplicate:AVX512_VEC (match_operand: 2 "nonimmediate_operand" "vm,xm,vm")) - (match_operand:SI 3 "const_int_operand" "n,n,n")))] + (match_operand:SI 3 "const_int_operand")))] "TARGET_AVX512F && (INTVAL (operands[3]) == (GET_MODE_UNIT_SIZE (mode) == 4 ? 0xFFF0 : 0xFC))" @@ -18143,7 +18143,7 @@ (match_operand:AVX512_VEC 1 "register_operand" "v") (vec_duplicate:AVX512_VEC (match_operand: 2 "nonimmediate_operand" "vm")) - (match_operand:SI 3 "const_int_operand" "n")))] + (match_operand:SI 3 "const_int_operand")))] "TARGET_AVX512F" { int mask; @@ -18811,7 +18811,7 @@ [(set (match_operand:V32HI 0 "register_operand" "=v") (unspec:V32HI [(match_operand:V32HI 1 "nonimmediate_operand" "vm") - (match_operand:SI 2 "const_0_to_255_operand" "n")] + (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_PSHUFLW))] "TARGET_AVX512BW" "vpshuflw\t{%2, %1, %0|%0, %1, %2}" @@ -18987,7 +18987,7 @@ [(set (match_operand:V32HI 0 "register_operand" "=v") (unspec:V32HI [(match_operand:V32HI 1 "nonimmediate_operand" "vm") - (match_operand:SI 2 "const_0_to_255_operand" "n")] + (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_PSHUFHW))] "TARGET_AVX512BW" "vpshufhw\t{%2, %1, %0|%0, %1, %2}" @@ -19665,7 +19665,7 @@ [(set (match_operand:VI124_128 0 "register_operand" "=v,x") (vec_concat:VI124_128 (match_operand: 1 "nonimmediate_operand" "vm,?!*y") - (match_operand: 2 "const0_operand" " C,C")))] + (match_operand: 2 "const0_operand")))] "TARGET_SSE2" "@ %vmovq\t{%1, %0|%0, %1} @@ -19739,7 +19739,7 @@ [(set (match_operand:V2DI 0 "register_operand" "=v,v ,x") (vec_concat:V2DI (match_operand:DI 1 "nonimmediate_operand" " r,vm,?!*y") - (match_operand:DI 2 "const0_operand" " C,C ,C")))] + (match_operand:DI 2 "const0_operand")))] "TARGET_SSE2" "@ * return HAVE_AS_IX86_INTERUNIT_MOVQ ? \"%vmovq\t{%1, %0|%0, %1}\" : \"%vmovd\t{%1, %0|%0, %1}\"; @@ -19763,7 +19763,7 @@ (vec_merge:VI8_AVX_AVX512F (vec_duplicate:VI8_AVX_AVX512F (match_operand: 2 "nonimmediate_operand" "r,vm")) - (match_operand:VI8_AVX_AVX512F 1 "const0_operand" "C,C") + (match_operand:VI8_AVX_AVX512F 1 "const0_operand") (const_int 1)))] "TARGET_AVX" "vmovq\t{%2, %x0|%x0, %2}" @@ -19964,7 +19964,7 @@ (unspec:SI [(lt:VF_128_256 (match_operand: 1 "register_operand" "x") - (match_operand: 2 "const0_operand" "C"))] + (match_operand: 2 "const0_operand"))] UNSPEC_MOVMSK))] "TARGET_SSE" "#" @@ -19982,7 +19982,7 @@ (unspec:SI [(lt:VF_128_256 (match_operand: 1 "register_operand" "x") - (match_operand: 2 "const0_operand" "C"))] + (match_operand: 2 "const0_operand"))] UNSPEC_MOVMSK)))] "TARGET_64BIT && TARGET_SSE" "#" @@ -20000,7 +20000,7 @@ [(subreg:VF_128_256 (ashiftrt: (match_operand: 1 "register_operand" "x") - (match_operand:QI 2 "const_int_operand" "n")) 0)] + (match_operand:QI 2 "const_int_operand")) 0)] UNSPEC_MOVMSK))] "TARGET_SSE" "#" @@ -20019,7 +20019,7 @@ [(subreg:VF_128_256 (ashiftrt: (match_operand: 1 "register_operand" "x") - (match_operand:QI 2 "const_int_operand" "n")) 0)] + (match_operand:QI 2 "const_int_operand")) 0)] UNSPEC_MOVMSK)))] "TARGET_64BIT && TARGET_SSE" "#" @@ -20160,7 +20160,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (unspec:SI [(lt:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand" "x") - (match_operand:VI1_AVX2 2 "const0_operand" "C"))] + (match_operand:VI1_AVX2 2 "const0_operand"))] UNSPEC_MOVMSK))] "TARGET_SSE2" "#" @@ -20182,7 +20182,7 @@ (zero_extend:DI (unspec:SI [(lt:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand" "x") - (match_operand:VI1_AVX2 2 "const0_operand" "C"))] + (match_operand:VI1_AVX2 2 "const0_operand"))] UNSPEC_MOVMSK)))] "TARGET_64BIT && TARGET_SSE2" "#" @@ -20204,7 +20204,7 @@ (sign_extend:DI (unspec:SI [(lt:V16QI (match_operand:V16QI 1 "register_operand" "x") - (match_operand:V16QI 2 "const0_operand" "C"))] + (match_operand:V16QI 2 "const0_operand"))] UNSPEC_MOVMSK)))] "TARGET_64BIT && TARGET_SSE2" "#" @@ -21003,7 +21003,7 @@ (unspec:VI1_AVX512 [(match_operand:VI1_AVX512 1 "register_operand" "v") (match_operand:VI1_AVX512 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")] + (match_operand:SI 3 "const_0_to_255_mul_8_operand")] UNSPEC_PALIGNR) (match_operand:VI1_AVX512 4 "nonimm_or_0_operand" "0C") (match_operand: 5 "register_operand" "Yk")))] @@ -21024,7 +21024,7 @@ (unspec:SSESCALARMODE [(match_operand:SSESCALARMODE 1 "register_operand" "0,") (match_operand:SSESCALARMODE 2 "vector_operand" "xBm,m") - (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")] + (match_operand:SI 3 "const_0_to_255_mul_8_operand")] UNSPEC_PALIGNR))] "TARGET_SSSE3" { @@ -21053,7 +21053,7 @@ [(set (match_operand:DI 0 "register_operand" "=y,x,Yv") (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv") (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yv") - (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n,n")] + (match_operand:SI 3 "const_0_to_255_mul_8_operand")] UNSPEC_PALIGNR))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" { @@ -21340,7 +21340,7 @@ (match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm") (lt:VF_128_256 (match_operand: 3 "register_operand" "Yz,Yz,x") - (match_operand: 4 "const0_operand" "C,C,C"))] + (match_operand: 4 "const0_operand"))] UNSPEC_BLENDV))] "TARGET_SSE4_1" "#" @@ -21372,7 +21372,7 @@ (subreg: (lt:VI48_AVX (match_operand:VI48_AVX 3 "register_operand" "Yz,Yz,x") - (match_operand:VI48_AVX 4 "const0_operand" "C,C,C")) 0)] + (match_operand:VI48_AVX 4 "const0_operand")) 0)] UNSPEC_BLENDV))] "TARGET_SSE4_1" "#" @@ -21427,7 +21427,7 @@ (unspec:VF_128_256 [(match_operand:VF_128_256 1 "vector_operand" "%0,0,x") (match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm") - (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_DP))] "TARGET_SSE4_1" "@ @@ -21465,7 +21465,7 @@ (unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,0,x") (match_operand:VI1_AVX2 2 "vector_operand" "YrBm,*xBm,xm") - (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_MPSADBW))] "TARGET_SSE4_1" "@ @@ -21554,7 +21554,7 @@ [(match_operand:VI1_AVX2 1 "register_operand" "0,0,x") (match_operand:VI1_AVX2 2 "vector_operand" "YrBm,*xBm,xm") (lt:VI1_AVX2 (match_operand:VI1_AVX2 3 "register_operand" "Yz,Yz,x") - (match_operand:VI1_AVX2 4 "const0_operand" "C,C,C"))] + (match_operand:VI1_AVX2 4 "const0_operand"))] UNSPEC_BLENDV))] "TARGET_SSE4_1" "#" @@ -21598,7 +21598,7 @@ (vec_merge:V8_128 (match_operand:V8_128 2 "vector_operand" "YrBm,*xBm,xm") (match_operand:V8_128 1 "register_operand" "0,0,x") - (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")))] + (match_operand:SI 3 "const_0_to_255_operand")))] "TARGET_SSE4_1" "@ pblendw\t{%3, %2, %0|%0, %2, %3} @@ -21670,7 +21670,7 @@ (vec_merge:V16_256 (match_operand:V16_256 2 "nonimmediate_operand" "xm") (match_operand:V16_256 1 "register_operand" "x") - (match_operand:SI 3 "avx2_pblendw_operand" "n")))] + (match_operand:SI 3 "avx2_pblendw_operand")))] "TARGET_AVX2" { operands[3] = GEN_INT (INTVAL (operands[3]) & 0xff); @@ -21687,7 +21687,7 @@ (vec_merge:VI4_AVX2 (match_operand:VI4_AVX2 2 "nonimmediate_operand" "xm") (match_operand:VI4_AVX2 1 "register_operand" "x") - (match_operand:SI 3 "const_0_to_255_operand" "n")))] + (match_operand:SI 3 "const_0_to_255_operand")))] "TARGET_AVX2" "vpblendd\t{%3, %2, %1, %0|%0, %1, %2, %3}" [(set_attr "type" "ssemov") @@ -21724,9 +21724,9 @@ (vec_select:V32QI (vec_concat:V64QI (match_operand:V32QI 1 "nonimmediate_operand" "vm") - (match_operand:V32QI 2 "const0_operand" "C")) + (match_operand:V32QI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" - [(match_operand 4 "const_int_operand" "n")])))] + [(match_operand 4 "const_int_operand")])))] "TARGET_AVX2" "#" "&& reload_completed" @@ -21743,10 +21743,10 @@ (subreg:V32QI (vec_concat:VI248_256 (match_operand: 1 "nonimmediate_operand" "vm") - (match_operand: 2 "const0_operand" "C")) 0) - (match_operand:V32QI 3 "const0_operand" "C")) + (match_operand: 2 "const0_operand")) 0) + (match_operand:V32QI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" - [(match_operand 5 "const_int_operand" "n")])))] + [(match_operand 5 "const_int_operand")])))] "TARGET_AVX2" "#" "&& reload_completed" @@ -21778,9 +21778,9 @@ (vec_select:V64QI (vec_concat:V128QI (match_operand:V64QI 1 "nonimmediate_operand" "vm") - (match_operand:V64QI 2 "const0_operand" "C")) + (match_operand:V64QI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" - [(match_operand 4 "const_int_operand" "n")])))] + [(match_operand 4 "const_int_operand")])))] "TARGET_AVX512BW" "#" "&& reload_completed" @@ -21797,10 +21797,10 @@ (subreg:V64QI (vec_concat:VI248_512 (match_operand: 1 "nonimmediate_operand" "vm") - (match_operand: 2 "const0_operand" "C")) 0) - (match_operand:V64QI 3 "const0_operand" "C")) + (match_operand: 2 "const0_operand")) 0) + (match_operand:V64QI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" - [(match_operand 5 "const_int_operand" "n")])))] + [(match_operand 5 "const_int_operand")])))] "TARGET_AVX512BW" "#" "&& reload_completed" @@ -21870,9 +21870,9 @@ (vec_select:V16QI (vec_concat:V32QI (match_operand:V16QI 1 "vector_operand" "YrBm,*xBm,Ywm") - (match_operand:V16QI 2 "const0_operand" "C,C,C")) + (match_operand:V16QI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" - [(match_operand 4 "const_int_operand" "n,n,n")])))] + [(match_operand 4 "const_int_operand")])))] "TARGET_SSE4_1" "#" "&& reload_completed" @@ -21903,10 +21903,10 @@ (subreg:V16QI (vec_concat:VI248_128 (match_operand: 1 "vector_operand" "YrBm,*xBm,Ywm") - (match_operand: 2 "const0_operand" "C,C,C")) 0) - (match_operand:V16QI 3 "const0_operand" "C,C,C")) + (match_operand: 2 "const0_operand")) 0) + (match_operand:V16QI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" - [(match_operand 5 "const_int_operand" "n,n,n")])))] + [(match_operand 5 "const_int_operand")])))] "TARGET_SSE4_1" "#" "&& reload_completed" @@ -22109,9 +22109,9 @@ (vec_select:V32HI (vec_concat:V64HI (match_operand:V32HI 1 "nonimmediate_operand" "vm") - (match_operand:V32HI 2 "const0_operand" "C")) + (match_operand:V32HI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" - [(match_operand 4 "const_int_operand" "n")])))] + [(match_operand 4 "const_int_operand")])))] "TARGET_AVX512F" "#" "&& reload_completed" @@ -22128,10 +22128,10 @@ (subreg:V32HI (vec_concat:VI148_512 (match_operand: 1 "nonimmediate_operand" "vm") - (match_operand: 2 "const0_operand" "C")) 0) - (match_operand:V32HI 3 "const0_operand" "C")) + (match_operand: 2 "const0_operand")) 0) + (match_operand:V32HI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" - [(match_operand 5 "const_int_operand" "n")])))] + [(match_operand 5 "const_int_operand")])))] "TARGET_AVX512F" "#" "&& reload_completed" @@ -22163,9 +22163,9 @@ (vec_select:V16HI (vec_concat:V32HI (match_operand:V16HI 1 "nonimmediate_operand" "vm") - (match_operand:V16HI 2 "const0_operand" "C")) + (match_operand:V16HI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" - [(match_operand 4 "const_int_operand" "n")])))] + [(match_operand 4 "const_int_operand")])))] "TARGET_AVX2" "#" "&& reload_completed" @@ -22182,10 +22182,10 @@ (subreg:V16HI (vec_concat:VI148_256 (match_operand: 1 "nonimmediate_operand" "vm") - (match_operand: 2 "const0_operand" "C")) 0) - (match_operand:V16HI 3 "const0_operand" "C")) + (match_operand: 2 "const0_operand")) 0) + (match_operand:V16HI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" - [(match_operand 5 "const_int_operand" "n")])))] + [(match_operand 5 "const_int_operand")])))] "TARGET_AVX2" "#" "&& reload_completed" @@ -22261,9 +22261,9 @@ (vec_select:V8HI (vec_concat:V16HI (match_operand:V8HI 1 "vector_operand" "YrBm,*xBm,vm") - (match_operand:V8HI 2 "const0_operand" "C,C,C")) + (match_operand:V8HI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" - [(match_operand 4 "const_int_operand" "n,n,n")])))] + [(match_operand 4 "const_int_operand")])))] "TARGET_SSE4_1" "#" "&& reload_completed" @@ -22292,10 +22292,10 @@ (subreg:V8HI (vec_concat:VI148_128 (match_operand: 1 "vector_operand" "YrBm,*xBm,vm") - (match_operand: 2 "const0_operand" "C,C,C")) 0) - (match_operand:V8HI 3 "const0_operand" "C,C,C")) + (match_operand: 2 "const0_operand")) 0) + (match_operand:V8HI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" - [(match_operand 5 "const_int_operand" "n,n,n")])))] + [(match_operand 5 "const_int_operand")])))] "TARGET_SSE4_1" "#" "&& reload_completed" @@ -22653,9 +22653,9 @@ (vec_select:V16SI (vec_concat:V32SI (match_operand:V16SI 1 "nonimmediate_operand" "vm") - (match_operand:V16SI 2 "const0_operand" "C")) + (match_operand:V16SI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" - [(match_operand 4 "const_int_operand" "n")])))] + [(match_operand 4 "const_int_operand")])))] "TARGET_AVX512F" "#" "&& reload_completed" @@ -22671,10 +22671,10 @@ (vec_concat:V32SI (vec_concat:V16SI (match_operand:V8SI 1 "nonimmediate_operand" "vm") - (match_operand:V8SI 2 "const0_operand" "C")) - (match_operand:V16SI 3 "const0_operand" "C")) + (match_operand:V8SI 2 "const0_operand")) + (match_operand:V16SI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" - [(match_operand 5 "const_int_operand" "n")])))] + [(match_operand 5 "const_int_operand")])))] "TARGET_AVX512F" "#" "&& reload_completed" @@ -22705,9 +22705,9 @@ (vec_select:V8SI (vec_concat:V16SI (match_operand:V8SI 1 "nonimmediate_operand" "vm") - (match_operand:V8SI 2 "const0_operand" "C")) + (match_operand:V8SI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" - [(match_operand 4 "const_int_operand" "n")])))] + [(match_operand 4 "const_int_operand")])))] "TARGET_AVX2" "#" "&& reload_completed" @@ -22723,10 +22723,10 @@ (vec_concat:V16SI (vec_concat:V8SI (match_operand:V4SI 1 "nonimmediate_operand" "vm") - (match_operand:V4SI 2 "const0_operand" "C")) - (match_operand:V8SI 3 "const0_operand" "C")) + (match_operand:V4SI 2 "const0_operand")) + (match_operand:V8SI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" - [(match_operand 5 "const_int_operand" "n")])))] + [(match_operand 5 "const_int_operand")])))] "TARGET_AVX2" "#" "&& reload_completed" @@ -22789,9 +22789,9 @@ (vec_select:V4SI (vec_concat:V8SI (match_operand:V4SI 1 "vector_operand" "YrBm,*xBm,vm") - (match_operand:V4SI 2 "const0_operand" "C,C,C")) + (match_operand:V4SI 2 "const0_operand")) (match_parallel 3 "pmovzx_parallel" - [(match_operand 4 "const_int_operand" "n,n,n")])))] + [(match_operand 4 "const_int_operand")])))] "TARGET_SSE4_1" "#" "&& reload_completed" @@ -22817,10 +22817,10 @@ (vec_concat:V8SI (vec_concat:V4SI (match_operand:V2SI 1 "vector_operand" "YrBm, *xBm, vm") - (match_operand:V2SI 2 "const0_operand" "C,C,C")) - (match_operand:V4SI 3 "const0_operand" "C,C,C")) + (match_operand:V2SI 2 "const0_operand")) + (match_operand:V4SI 3 "const0_operand")) (match_parallel 4 "pmovzx_parallel" - [(match_operand 5 "const_int_operand" "n,n,n")])))] + [(match_operand 5 "const_int_operand")])))] "TARGET_SSE4_1" "#" "&& reload_completed" @@ -22924,7 +22924,7 @@ [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (unspec:VF_128_256 [(match_operand:VF_128_256 1 "vector_operand" "YrBm,*xBm,xm") - (match_operand:SI 2 "const_0_to_15_operand" "n,n,n")] + (match_operand:SI 2 "const_0_to_15_operand")] UNSPEC_ROUND))] "TARGET_SSE4_1" "%vround\t{%2, %1, %0|%0, %1, %2}" @@ -23017,7 +23017,7 @@ (vec_merge:VF_128 (unspec:VF_128 [(match_operand:VF_128 2 "nonimmediate_operand" "Yrm,*xm,xm,vm") - (match_operand:SI 3 "const_0_to_15_operand" "n,n,n,n")] + (match_operand:SI 3 "const_0_to_15_operand")] UNSPEC_ROUND) (match_operand:VF_128 1 "register_operand" "0,0,x,v") (const_int 1)))] @@ -23041,7 +23041,7 @@ (vec_duplicate:VFH_128 (unspec: [(match_operand: 2 "nonimmediate_operand" "Yrm,*xm,xm,vm") - (match_operand:SI 3 "const_0_to_15_operand" "n,n,n,n")] + (match_operand:SI 3 "const_0_to_15_operand")] UNSPEC_ROUND)) (match_operand:VFH_128 1 "register_operand" "0,0,x,v") (const_int 1)))] @@ -23154,7 +23154,7 @@ (match_operand:SI 3 "register_operand" "a,a") (match_operand:V16QI 4 "nonimmediate_operand" "x,m") (match_operand:SI 5 "register_operand" "d,d") - (match_operand:SI 6 "const_0_to_255_operand" "n,n")] + (match_operand:SI 6 "const_0_to_255_operand")] UNSPEC_PCMPESTR)) (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz") (unspec:V16QI @@ -23214,7 +23214,7 @@ (match_operand:SI 2 "register_operand" "a,a") (match_operand:V16QI 3 "nonimmediate_operand" "x,m") (match_operand:SI 4 "register_operand" "d,d") - (match_operand:SI 5 "const_0_to_255_operand" "n,n")] + (match_operand:SI 5 "const_0_to_255_operand")] UNSPEC_PCMPESTR)) (set (reg:CC FLAGS_REG) (unspec:CC @@ -23242,7 +23242,7 @@ (match_operand:SI 2 "register_operand" "a,a") (match_operand:V16QI 3 "nonimmediate_operand" "x,m") (match_operand:SI 4 "register_operand" "d,d") - (match_operand:SI 5 "const_0_to_255_operand" "n,n")] + (match_operand:SI 5 "const_0_to_255_operand")] UNSPEC_PCMPESTR)) (set (reg:CC FLAGS_REG) (unspec:CC @@ -23270,7 +23270,7 @@ (match_operand:SI 3 "register_operand" "a,a,a,a") (match_operand:V16QI 4 "nonimmediate_operand" "x,m,x,m") (match_operand:SI 5 "register_operand" "d,d,d,d") - (match_operand:SI 6 "const_0_to_255_operand" "n,n,n,n")] + (match_operand:SI 6 "const_0_to_255_operand")] UNSPEC_PCMPESTR)) (clobber (match_scratch:V16QI 0 "=Yz,Yz,X,X")) (clobber (match_scratch:SI 1 "= X, X,c,c"))] @@ -23294,7 +23294,7 @@ (unspec:SI [(match_operand:V16QI 2 "register_operand" "x,x") (match_operand:V16QI 3 "nonimmediate_operand" "x,m") - (match_operand:SI 4 "const_0_to_255_operand" "n,n")] + (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_PCMPISTR)) (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz") (unspec:V16QI @@ -23345,7 +23345,7 @@ (unspec:SI [(match_operand:V16QI 1 "register_operand" "x,x") (match_operand:V16QI 2 "nonimmediate_operand" "x,m") - (match_operand:SI 3 "const_0_to_255_operand" "n,n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_PCMPISTR)) (set (reg:CC FLAGS_REG) (unspec:CC @@ -23369,7 +23369,7 @@ (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x,x") (match_operand:V16QI 2 "nonimmediate_operand" "x,m") - (match_operand:SI 3 "const_0_to_255_operand" "n,n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_PCMPISTR)) (set (reg:CC FLAGS_REG) (unspec:CC @@ -23393,7 +23393,7 @@ (unspec:CC [(match_operand:V16QI 2 "register_operand" "x,x,x,x") (match_operand:V16QI 3 "nonimmediate_operand" "x,m,x,m") - (match_operand:SI 4 "const_0_to_255_operand" "n,n,n,n")] + (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_PCMPISTR)) (clobber (match_scratch:V16QI 0 "=Yz,Yz,X,X")) (clobber (match_scratch:SI 1 "= X, X,c,c"))] @@ -23440,9 +23440,9 @@ [(unspec:P [(match_operand:P 2 "vsib_address_operand" "Tv") (match_operand:VI48_512 1 "register_operand" "v") - (match_operand:SI 3 "const1248_operand" "n")] + (match_operand:SI 3 "const1248_operand")] UNSPEC_VSIBADDR)]) - (match_operand:SI 4 "const_2_to_3_operand" "n")] + (match_operand:SI 4 "const_2_to_3_operand")] UNSPEC_GATHER_PREFETCH)] "TARGET_AVX512PF" { @@ -23487,9 +23487,9 @@ [(unspec:P [(match_operand:P 2 "vsib_address_operand" "Tv") (match_operand:VI4_256_8_512 1 "register_operand" "v") - (match_operand:SI 3 "const1248_operand" "n")] + (match_operand:SI 3 "const1248_operand")] UNSPEC_VSIBADDR)]) - (match_operand:SI 4 "const_2_to_3_operand" "n")] + (match_operand:SI 4 "const_2_to_3_operand")] UNSPEC_GATHER_PREFETCH)] "TARGET_AVX512PF" { @@ -23534,9 +23534,9 @@ [(unspec:P [(match_operand:P 2 "vsib_address_operand" "Tv") (match_operand:VI48_512 1 "register_operand" "v") - (match_operand:SI 3 "const1248_operand" "n")] + (match_operand:SI 3 "const1248_operand")] UNSPEC_VSIBADDR)]) - (match_operand:SI 4 "const2367_operand" "n")] + (match_operand:SI 4 "const2367_operand")] UNSPEC_SCATTER_PREFETCH)] "TARGET_AVX512PF" { @@ -23583,9 +23583,9 @@ [(unspec:P [(match_operand:P 2 "vsib_address_operand" "Tv") (match_operand:VI4_256_8_512 1 "register_operand" "v") - (match_operand:SI 3 "const1248_operand" "n")] + (match_operand:SI 3 "const1248_operand")] UNSPEC_VSIBADDR)]) - (match_operand:SI 4 "const2367_operand" "n")] + (match_operand:SI 4 "const2367_operand")] UNSPEC_SCATTER_PREFETCH)] "TARGET_AVX512PF" { @@ -24123,7 +24123,7 @@ [(set (match_operand:VI_128 0 "register_operand" "=x") (rotate:VI_128 (match_operand:VI_128 1 "nonimmediate_operand" "xm") - (match_operand:SI 2 "const_0_to__operand" "n")))] + (match_operand:SI 2 "const_0_to__operand")))] "TARGET_XOP" "vprot\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseishft") @@ -24134,7 +24134,7 @@ [(set (match_operand:VI_128 0 "register_operand" "=x") (rotatert:VI_128 (match_operand:VI_128 1 "nonimmediate_operand" "xm") - (match_operand:SI 2 "const_0_to__operand" "n")))] + (match_operand:SI 2 "const_0_to__operand")))] "TARGET_XOP" { operands[3] @@ -24740,7 +24740,7 @@ (unspec:VI_128 [(match_operand:VI_128 1 "register_operand" "x") (match_operand:VI_128 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_int_operand" "n")] + (match_operand:SI 3 "const_int_operand")] UNSPEC_XOP_TRUEFALSE))] "TARGET_XOP" { @@ -24760,7 +24760,7 @@ [(match_operand:VF_128_256 1 "register_operand" "x,x") (match_operand:VF_128_256 2 "nonimmediate_operand" "x,m") (match_operand: 3 "nonimmediate_operand" "xm,x") - (match_operand:SI 4 "const_0_to_3_operand" "n,n")] + (match_operand:SI 4 "const_0_to_3_operand")] UNSPEC_VPERMIL2))] "TARGET_XOP" "vpermil2\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}" @@ -24848,7 +24848,7 @@ (define_insn "aeskeygenassist" [(set (match_operand:V2DI 0 "register_operand" "=x") (unspec:V2DI [(match_operand:V2DI 1 "vector_operand" "xBm") - (match_operand:SI 2 "const_0_to_255_operand" "n")] + (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_AESKEYGENASSIST))] "TARGET_AES" "%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}" @@ -24862,7 +24862,7 @@ [(set (match_operand:V2DI 0 "register_operand" "=x,x") (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x") (match_operand:V2DI 2 "vector_operand" "xBm,xm") - (match_operand:SI 3 "const_0_to_255_operand" "n,n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_PCLMUL))] "TARGET_PCLMUL" "@ @@ -25314,7 +25314,7 @@ (unspec:V4DI [(match_operand:V4DI 1 "register_operand" "x") (match_operand:V4DI 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_VPERMTI))] "TARGET_AVX2" "vperm2i128\t{%3, %2, %1, %0|%0, %1, %2, %3}" @@ -25858,7 +25858,7 @@ (unspec:AVX256MODE2P [(match_operand:AVX256MODE2P 1 "register_operand" "x") (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "xm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_VPERMIL2F128))] "TARGET_AVX" "vperm2\t{%3, %2, %1, %0|%0, %1, %2, %3}" @@ -25898,7 +25898,7 @@ (vec_select:V_128 (match_operand:V_128 1 "register_operand" "0,Yw") (match_parallel 2 "palignr_operand" - [(match_operand 3 "const_int_operand" "n,n")])))] + [(match_operand 3 "const_int_operand")])))] "TARGET_SSSE3" { operands[2] = (GEN_INT (INTVAL (operands[3]) @@ -26568,7 +26568,7 @@ [(set (match_operand:V8HI 0 "register_operand" "=v") (vec_concat:V8HI (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:SI 2 "const_0_to_255_operand" "N")] + (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH) (match_operand:V4HI 3 "const0_operand")))] "(TARGET_F16C || TARGET_AVX512VL) && " @@ -26580,7 +26580,7 @@ (define_insn "*vcvtps2ph_store" [(set (match_operand:V4HI 0 "memory_operand" "=m") (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:SI 2 "const_0_to_255_operand" "N")] + (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH))] "TARGET_F16C || TARGET_AVX512VL" "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" @@ -26591,7 +26591,7 @@ (define_insn "vcvtps2ph256" [(set (match_operand:V8HI 0 "register_operand" "=v") (unspec:V8HI [(match_operand:V8SF 1 "register_operand" "v") - (match_operand:SI 2 "const_0_to_255_operand" "N")] + (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH))] "TARGET_F16C || TARGET_AVX512VL" "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" @@ -26603,7 +26603,7 @@ (define_insn "*vcvtps2ph256" [(set (match_operand:V8HI 0 "memory_operand" "=m") (unspec:V8HI [(match_operand:V8SF 1 "register_operand" "v") - (match_operand:SI 2 "const_0_to_255_operand" "N")] + (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH))] "TARGET_F16C || TARGET_AVX512VL" "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" @@ -26616,7 +26616,7 @@ [(set (match_operand:V16HI 0 "register_operand" "=v") (unspec:V16HI [(match_operand:V16SF 1 "register_operand" "v") - (match_operand:SI 2 "const_0_to_255_operand" "N")] + (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH))] "TARGET_AVX512F" "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" @@ -26628,7 +26628,7 @@ [(set (match_operand:V16HI 0 "memory_operand" "=m") (unspec:V16HI [(match_operand:V16SF 1 "register_operand" "v") - (match_operand:SI 2 "const_0_to_255_operand" "N")] + (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_VCVTPS2PH))] "TARGET_AVX512F" "vcvtps2ph\t{%2, %1, %0|%0, %1, %2}" @@ -26686,7 +26686,7 @@ [(unspec:P [(match_operand:P 3 "vsib_address_operand" "Tv") (match_operand: 4 "register_operand" "x") - (match_operand:SI 6 "const1248_operand" "n")] + (match_operand:SI 6 "const1248_operand")] UNSPEC_VSIBADDR)]) (mem:BLK (scratch)) (match_operand:VEC_GATHER_MODE 5 "register_operand" "1")] @@ -26706,7 +26706,7 @@ [(unspec:P [(match_operand:P 2 "vsib_address_operand" "Tv") (match_operand: 3 "register_operand" "x") - (match_operand:SI 5 "const1248_operand" "n")] + (match_operand:SI 5 "const1248_operand")] UNSPEC_VSIBADDR)]) (mem:BLK (scratch)) (match_operand:VEC_GATHER_MODE 4 "register_operand" "1")] @@ -26747,7 +26747,7 @@ [(unspec:P [(match_operand:P 3 "vsib_address_operand" "Tv") (match_operand: 4 "register_operand" "x") - (match_operand:SI 6 "const1248_operand" "n")] + (match_operand:SI 6 "const1248_operand")] UNSPEC_VSIBADDR)]) (mem:BLK (scratch)) (match_operand: 5 "register_operand" "1")] @@ -26767,7 +26767,7 @@ [(unspec:P [(match_operand:P 2 "vsib_address_operand" "Tv") (match_operand: 3 "register_operand" "x") - (match_operand:SI 5 "const1248_operand" "n")] + (match_operand:SI 5 "const1248_operand")] UNSPEC_VSIBADDR)]) (mem:BLK (scratch)) (match_operand: 4 "register_operand" "1")] @@ -26792,7 +26792,7 @@ [(unspec:P [(match_operand:P 3 "vsib_address_operand" "Tv") (match_operand: 4 "register_operand" "x") - (match_operand:SI 6 "const1248_operand" "n")] + (match_operand:SI 6 "const1248_operand")] UNSPEC_VSIBADDR)]) (mem:BLK (scratch)) (match_operand: 5 "register_operand" "1")] @@ -26815,7 +26815,7 @@ [(unspec:P [(match_operand:P 2 "vsib_address_operand" "Tv") (match_operand: 3 "register_operand" "x") - (match_operand:SI 5 "const1248_operand" "n")] + (match_operand:SI 5 "const1248_operand")] UNSPEC_VSIBADDR)]) (mem:BLK (scratch)) (match_operand: 4 "register_operand" "1")] @@ -26857,7 +26857,7 @@ [(unspec:P [(match_operand:P 4 "vsib_address_operand" "Tv") (match_operand: 3 "register_operand" "v") - (match_operand:SI 5 "const1248_operand" "n")] + (match_operand:SI 5 "const1248_operand")] UNSPEC_VSIBADDR)])] UNSPEC_GATHER)) (clobber (match_scratch: 2 "=&Yk"))] @@ -26878,7 +26878,7 @@ [(unspec:P [(match_operand:P 3 "vsib_address_operand" "Tv") (match_operand: 2 "register_operand" "v") - (match_operand:SI 4 "const1248_operand" "n")] + (match_operand:SI 4 "const1248_operand")] UNSPEC_VSIBADDR)])] UNSPEC_GATHER)) (clobber (match_scratch: 1 "=&Yk"))] @@ -26919,7 +26919,7 @@ [(unspec:P [(match_operand:P 4 "vsib_address_operand" "Tv") (match_operand: 3 "register_operand" "v") - (match_operand:SI 5 "const1248_operand" "n")] + (match_operand:SI 5 "const1248_operand")] UNSPEC_VSIBADDR)])] UNSPEC_GATHER)) (clobber (match_scratch:QI 2 "=&Yk"))] @@ -26940,7 +26940,7 @@ [(unspec:P [(match_operand:P 3 "vsib_address_operand" "Tv") (match_operand: 2 "register_operand" "v") - (match_operand:SI 4 "const1248_operand" "n")] + (match_operand:SI 4 "const1248_operand")] UNSPEC_VSIBADDR)])] UNSPEC_GATHER)) (clobber (match_scratch:QI 1 "=&Yk"))] @@ -26985,7 +26985,7 @@ [(unspec:P [(match_operand:P 0 "vsib_address_operand" "Tv") (match_operand: 2 "register_operand" "v") - (match_operand:SI 4 "const1248_operand" "n") + (match_operand:SI 4 "const1248_operand") (match_operand: 6 "register_operand" "1")] UNSPEC_VSIBADDR)]) (unspec:VI48F @@ -27025,7 +27025,7 @@ [(unspec:P [(match_operand:P 0 "vsib_address_operand" "Tv") (match_operand: 2 "register_operand" "v") - (match_operand:SI 4 "const1248_operand" "n") + (match_operand:SI 4 "const1248_operand") (match_operand:QI 6 "register_operand" "1")] UNSPEC_VSIBADDR)]) (unspec:VI48F @@ -27246,7 +27246,7 @@ [(set (match_operand: 0 "register_operand" "=k") (unspec: [(match_operand:VFH_AVX512VL 1 "vector_operand" "vm") - (match_operand 2 "const_0_to_255_operand" "n")] + (match_operand 2 "const_0_to_255_operand")] UNSPEC_FPCLASS))] "TARGET_AVX512DQ || VALID_AVX512FP16_REG_MODE(mode)" "vfpclass\t{%2, %1, %0|%0, %1, %2}"; @@ -27260,7 +27260,7 @@ (and: (unspec: [(match_operand:VFH_128 1 "nonimmediate_operand" "vm") - (match_operand 2 "const_0_to_255_operand" "n")] + (match_operand 2 "const_0_to_255_operand")] UNSPEC_FPCLASS) (const_int 1)))] "TARGET_AVX512DQ || VALID_AVX512FP16_REG_MODE(mode)" @@ -27384,7 +27384,7 @@ (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "0") (match_operand:V4SI 2 "vector_operand" "xBm") - (match_operand:SI 3 "const_0_to_3_operand" "n")] + (match_operand:SI 3 "const_0_to_3_operand")] UNSPEC_SHA1RNDS4))] "TARGET_SHA" "sha1rnds4\t{%3, %2, %0|%0, %2, %3}" @@ -27611,7 +27611,7 @@ [(match_operand:V16SF 1 "register_operand" "0") (match_operand:V64SF 2 "register_operand" "v") (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD) - (match_operand:V16SF 4 "const0_operand" "C") + (match_operand:V16SF 4 "const0_operand") (match_operand:HI 5 "register_operand" "Yk")))] "TARGET_AVX5124FMAPS" "v4fmaddps\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}" @@ -27652,7 +27652,7 @@ [(match_operand:V4SF 1 "register_operand" "0") (match_operand:V64SF 2 "register_operand" "v") (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD) - (match_operand:V4SF 4 "const0_operand" "C") + (match_operand:V4SF 4 "const0_operand") (match_operand:QI 5 "register_operand" "Yk")))] "TARGET_AVX5124FMAPS" "v4fmaddss\t{%3, %x2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %x2, %3}" @@ -27693,7 +27693,7 @@ [(match_operand:V16SF 1 "register_operand" "0") (match_operand:V64SF 2 "register_operand" "v") (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD) - (match_operand:V16SF 4 "const0_operand" "C") + (match_operand:V16SF 4 "const0_operand") (match_operand:HI 5 "register_operand" "Yk")))] "TARGET_AVX5124FMAPS" "v4fnmaddps\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}" @@ -27734,7 +27734,7 @@ [(match_operand:V4SF 1 "register_operand" "0") (match_operand:V64SF 2 "register_operand" "v") (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD) - (match_operand:V4SF 4 "const0_operand" "C") + (match_operand:V4SF 4 "const0_operand") (match_operand:QI 5 "register_operand" "Yk")))] "TARGET_AVX5124FMAPS" "v4fnmaddss\t{%3, %x2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %x2, %3}" @@ -27775,7 +27775,7 @@ [(match_operand:V16SI 1 "register_operand" "0") (match_operand:V64SI 2 "register_operand" "v") (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSD) - (match_operand:V16SI 4 "const0_operand" "C") + (match_operand:V16SI 4 "const0_operand") (match_operand:HI 5 "register_operand" "Yk")))] "TARGET_AVX5124VNNIW" "vp4dpwssd\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}" @@ -27816,7 +27816,7 @@ [(match_operand:V16SI 1 "register_operand" "0") (match_operand:V64SI 2 "register_operand" "v") (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSDS) - (match_operand:V16SI 4 "const0_operand" "C") + (match_operand:V16SI 4 "const0_operand") (match_operand:HI 5 "register_operand" "Yk")))] "TARGET_AVX5124VNNIW" "vp4dpwssds\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}" @@ -27892,7 +27892,7 @@ (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "0,v") (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm") - (match_operand 3 "const_0_to_255_operand" "n,n")] + (match_operand 3 "const_0_to_255_operand")] UNSPEC_GF2P8AFFINEINV))] "TARGET_GFNI" "@ @@ -27909,7 +27909,7 @@ (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "0,v") (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm") - (match_operand 3 "const_0_to_255_operand" "n,n")] + (match_operand 3 "const_0_to_255_operand")] UNSPEC_GF2P8AFFINE))] "TARGET_GFNI" "@ @@ -27942,7 +27942,7 @@ (unspec:VI248_AVX512VL [(match_operand:VI248_AVX512VL 1 "register_operand" "v") (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_VPSHRD))] "TARGET_AVX512VBMI2" "vpshrd\t{%3, %2, %1, %0|%0, %1, %2, %3 }" @@ -27953,7 +27953,7 @@ (unspec:VI248_AVX512VL [(match_operand:VI248_AVX512VL 1 "register_operand" "v") (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_VPSHLD))] "TARGET_AVX512VBMI2" "vpshld\t{%3, %2, %1, %0|%0, %1, %2, %3 }" @@ -28009,7 +28009,7 @@ (match_operand:VI248_AVX512VL 2 "register_operand" "v") (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHRDV) - (match_operand:VI248_AVX512VL 4 "const0_operand" "C") + (match_operand:VI248_AVX512VL 4 "const0_operand") (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VBMI2" "vpshrdv\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" @@ -28066,7 +28066,7 @@ (match_operand:VI248_AVX512VL 2 "register_operand" "v") (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPSHLDV) - (match_operand:VI248_AVX512VL 4 "const0_operand" "C") + (match_operand:VI248_AVX512VL 4 "const0_operand") (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VBMI2" "vpshldv\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" @@ -28162,7 +28162,7 @@ (match_operand:VI4_AVX512VL 2 "register_operand" "v") (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm") ] UNSPEC_VPMADDUBSWACCD) - (match_operand:VI4_AVX512VL 4 "const0_operand" "C") + (match_operand:VI4_AVX512VL 4 "const0_operand") (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpbusd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" @@ -28230,7 +28230,7 @@ (match_operand:VI4_AVX512VL 2 "register_operand" "v") (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPMADDUBSWACCSSD) - (match_operand:VI4_AVX512VL 4 "const0_operand" "C") + (match_operand:VI4_AVX512VL 4 "const0_operand") (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpbusds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" @@ -28298,7 +28298,7 @@ (match_operand:VI4_AVX512VL 2 "register_operand" "v") (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPMADDWDACCD) - (match_operand:VI4_AVX512VL 4 "const0_operand" "C") + (match_operand:VI4_AVX512VL 4 "const0_operand") (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpwssd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" @@ -28366,7 +28366,7 @@ (match_operand:VI4_AVX512VL 2 "register_operand" "v") (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")] UNSPEC_VPMADDWDACCSSD) - (match_operand:VI4_AVX512VL 4 "const0_operand" "C") + (match_operand:VI4_AVX512VL 4 "const0_operand") (match_operand: 5 "register_operand" "Yk")))] "TARGET_AVX512VNNI" "vpdpwssds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }" @@ -28416,7 +28416,7 @@ [(set (match_operand:VI8_FVL 0 "register_operand" "=v") (unspec:VI8_FVL [(match_operand:VI8_FVL 1 "register_operand" "v") (match_operand:VI8_FVL 2 "vector_operand" "vm") - (match_operand:SI 3 "const_0_to_255_operand" "n")] + (match_operand:SI 3 "const_0_to_255_operand")] UNSPEC_VPCLMULQDQ))] "TARGET_VPCLMULQDQ" "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}" diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md index bb86f82905f..0b7588237fe 100644 --- a/gcc/config/i386/subst.md +++ b/gcc/config/i386/subst.md @@ -137,7 +137,7 @@ [(set (match_dup 0) (vec_merge:SUBST_V (match_dup 1) - (match_operand:SUBST_V 2 "const0_operand" "C") + (match_operand:SUBST_V 2 "const0_operand") (match_operand: 3 "register_operand" "Yk"))) ]) @@ -155,7 +155,7 @@ (vec_merge:SUBST_V (vec_merge:SUBST_V (match_dup 1) - (match_operand:SUBST_V 3 "const0_operand" "C") + (match_operand:SUBST_V 3 "const0_operand") (match_operand: 4 "register_operand" "Yk")) (match_dup 2) (const_int 1)))]) @@ -171,7 +171,7 @@ [(set (match_dup 0) (vec_merge:SUBST_CV (match_dup 1) - (match_operand:SUBST_CV 2 "const0_operand" "C") + (match_operand:SUBST_CV 2 "const0_operand") (unspec: [(match_operand: 3 "register_operand" "Yk")] UNSPEC_COMPLEX_MASK))) @@ -372,7 +372,7 @@ (vec_merge:SUBST_CV (vec_merge:SUBST_CV (match_dup 1) - (match_operand:SUBST_CV 3 "const0_operand" "C") + (match_operand:SUBST_CV 3 "const0_operand") (unspec: [(match_operand: 4 "register_operand" "Yk")] UNSPEC_COMPLEX_MASK)) @@ -478,5 +478,5 @@ [(set (match_dup 0) (vec_merge:SUBST_V (match_dup 1) - (match_operand:SUBST_V 2 "const0_operand" "C") + (match_operand:SUBST_V 2 "const0_operand") (match_operand: 3 "register_operand" "Yk")))]) diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index 820e9ca911a..92634d538cb 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -745,10 +745,10 @@ [(match_operand:SWI 0 "memory_operand" "+m") (match_operand:SI 3 "const_int_operand")] ;; model UNSPECV_XCHG) - (match_operand:SWI 2 "const_int_operand" "i"))) + (match_operand:SWI 2 "const_int_operand"))) (set (match_dup 0) (plus:SWI (match_dup 0) - (match_operand:SWI 1 "const_int_operand" "i")))] + (match_operand:SWI 1 "const_int_operand")))] "(unsigned HOST_WIDE_INT) INTVAL (operands[1]) == -(unsigned HOST_WIDE_INT) INTVAL (operands[2])" {