From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7808) id DBC07385AE47; Thu, 9 Jun 2022 05:32:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DBC07385AE47 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: HaoChen Gui To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-1020] This patch replaces shift and ior insns with one rotate and mask insn for the split patterns which a X-Act-Checkin: gcc X-Git-Author: Haochen Gui X-Git-Refname: refs/heads/master X-Git-Oldrev: 02b4e2de3204e74ce06d2d46bc8ee30ac93ce9fb X-Git-Newrev: 2fc6e3d55f6080da3a43243f595bd1266595127d Message-Id: <20220609053216.DBC07385AE47@sourceware.org> Date: Thu, 9 Jun 2022 05:32:16 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Jun 2022 05:32:17 -0000 https://gcc.gnu.org/g:2fc6e3d55f6080da3a43243f595bd1266595127d commit r13-1020-g2fc6e3d55f6080da3a43243f595bd1266595127d Author: Haochen Gui Date: Thu Jun 9 13:24:15 2022 +0800 This patch replaces shift and ior insns with one rotate and mask insn for the split patterns which are for DI byte swap on Power6. gcc/ * config/rs6000/rs6000.md (define_split for bswapdi load): Merge shift and ior insns to one rotate and mask insn. (define_split for bswapdi register): Likewise. gcc/testsuite/ * gcc.target/powerpc/pr93453-1.c: New. Diff: --- gcc/config/rs6000/rs6000.md | 12 ++++++------ gcc/testsuite/gcc.target/powerpc/pr93453-1.c | 14 ++++++++++++++ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3eca448a262..1c125f07e89 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2841,8 +2841,8 @@ emit_insn (gen_bswapsi2 (dest_32, word2)); } - emit_insn (gen_ashldi3 (op3, op3, GEN_INT (32))); - emit_insn (gen_iordi3 (dest, dest, op3)); + emit_insn (gen_rotldi3_insert_3 (dest, op3, GEN_INT (32), dest, + GEN_INT (0xffffffff))); DONE; }) @@ -2927,10 +2927,10 @@ rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off); emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32))); - emit_insn (gen_bswapsi2 (dest_si, src_si)); - emit_insn (gen_bswapsi2 (op3_si, op2_si)); - emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32))); - emit_insn (gen_iordi3 (dest, dest, op3)); + emit_insn (gen_bswapsi2 (op3_si, src_si)); + emit_insn (gen_bswapsi2 (dest_si, op2_si)); + emit_insn (gen_rotldi3_insert_3 (dest, op3, GEN_INT (32), dest, + GEN_INT (0xffffffff))); DONE; }) diff --git a/gcc/testsuite/gcc.target/powerpc/pr93453-1.c b/gcc/testsuite/gcc.target/powerpc/pr93453-1.c new file mode 100644 index 00000000000..b396458ba12 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr93453-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile { target has_arch_ppc64 } } */ +/* { dg-options "-mdejagnu-cpu=power6 -O2" } */ + +unsigned long load_byte_reverse (unsigned long *in) +{ + return __builtin_bswap64 (*in); +} + +unsigned long byte_reverse (unsigned long in) +{ + return __builtin_bswap64 (in); +} + +/* { dg-final { scan-assembler-times {\mrldimi\M} 2 } } */