From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1880) id 1C90F385DC05; Thu, 9 Jun 2022 22:10:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1C90F385DC05 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Max Filippov To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-1034] xtensa: Add clrsbsi2 insn pattern X-Act-Checkin: gcc X-Git-Author: Takayuki 'January June' Suwa X-Git-Refname: refs/heads/master X-Git-Oldrev: e44e7face13f38f9b228e2619786ba0add9ef77b X-Git-Newrev: 29dc90a580bf45f503ed89eb1dc63b5676db776b Message-Id: <20220609221031.1C90F385DC05@sourceware.org> Date: Thu, 9 Jun 2022 22:10:31 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Jun 2022 22:10:31 -0000 https://gcc.gnu.org/g:29dc90a580bf45f503ed89eb1dc63b5676db776b commit r13-1034-g29dc90a580bf45f503ed89eb1dc63b5676db776b Author: Takayuki 'January June' Suwa Date: Sun May 29 19:57:35 2022 +0900 xtensa: Add clrsbsi2 insn pattern > (clrsb:m x) > Represents the number of redundant leading sign bits in x, represented > as an integer of mode m, starting at the most significant bit position. This explanation is just what the NSA instruction (not ever emitted before) calculates in Xtensa ISA. gcc/ChangeLog: * config/xtensa/xtensa.md (clrsbsi2): New insn pattern. libgcc/ChangeLog: * config/xtensa/lib1funcs.S (__clrsbsi2): New function. * config/xtensa/t-xtensa (LIB1ASMFUNCS): Add _clrsbsi2. Diff: --- gcc/config/xtensa/xtensa.md | 12 +++++++++++- libgcc/config/xtensa/lib1funcs.S | 23 +++++++++++++++++++++++ libgcc/config/xtensa/t-xtensa | 2 +- 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 3afc252323b..8ff6f9a95fe 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -429,7 +429,17 @@ (set_attr "length" "3")]) -;; Count leading/trailing zeros and find first bit. +;; Count redundant leading sign bits and leading/trailing zeros, +;; and find first bit. + +(define_insn "clrsbsi2" + [(set (match_operand:SI 0 "register_operand" "=a") + (clrsb:SI (match_operand:SI 1 "register_operand" "r")))] + "TARGET_NSA" + "nsa\t%0, %1" + [(set_attr "type" "arith") + (set_attr "mode" "SI") + (set_attr "length" "3")]) (define_insn "clzsi2" [(set (match_operand:SI 0 "register_operand" "=a") diff --git a/libgcc/config/xtensa/lib1funcs.S b/libgcc/config/xtensa/lib1funcs.S index 5a2bd20534f..3932d206256 100644 --- a/libgcc/config/xtensa/lib1funcs.S +++ b/libgcc/config/xtensa/lib1funcs.S @@ -456,6 +456,29 @@ __nsau_data: #endif /* L_clz */ +#ifdef L_clrsbsi2 + .align 4 + .global __clrsbsi2 + .type __clrsbsi2, @function +__clrsbsi2: + leaf_entry sp, 16 +#if XCHAL_HAVE_NSA + nsa a2, a2 +#else + srai a3, a2, 31 + xor a3, a3, a2 + movi a2, 31 + beqz a3, .Lreturn + do_nsau a2, a3, a4, a5 + addi a2, a2, -1 +.Lreturn: +#endif + leaf_return + .size __clrsbsi2, . - __clrsbsi2 + +#endif /* L_clrsbsi2 */ + + #ifdef L_clzsi2 .align 4 .global __clzsi2 diff --git a/libgcc/config/xtensa/t-xtensa b/libgcc/config/xtensa/t-xtensa index 9836c96aefc..084618b382e 100644 --- a/libgcc/config/xtensa/t-xtensa +++ b/libgcc/config/xtensa/t-xtensa @@ -1,6 +1,6 @@ LIB1ASMSRC = xtensa/lib1funcs.S LIB1ASMFUNCS = _mulsi3 _divsi3 _modsi3 _udivsi3 _umodsi3 \ - _umulsidi3 _clz _clzsi2 _ctzsi2 _ffssi2 \ + _umulsidi3 _clz _clrsbsi2 _clzsi2 _ctzsi2 _ffssi2 \ _ashldi3 _ashrdi3 _lshrdi3 \ _bswapsi2 _bswapdi2 \ _negsf2 _addsubsf3 _mulsf3 _divsf3 _cmpsf2 _fixsfsi _fixsfdi \