From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1251) id 42E0B3825BC8; Fri, 10 Jun 2022 14:20:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 42E0B3825BC8 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Roger Sayle To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-1038] PR rtl-optimization/7061: Complex number arguments on x86_64-like ABIs. X-Act-Checkin: gcc X-Git-Author: Roger Sayle X-Git-Refname: refs/heads/master X-Git-Oldrev: b370ed0bf93ecf0ff51d29e7fc132c433b2aa1be X-Git-Newrev: 1753a7120109c1d3b682f9487d6cca64fb2f0929 Message-Id: <20220610142012.42E0B3825BC8@sourceware.org> Date: Fri, 10 Jun 2022 14:20:12 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Jun 2022 14:20:12 -0000 https://gcc.gnu.org/g:1753a7120109c1d3b682f9487d6cca64fb2f0929 commit r13-1038-g1753a7120109c1d3b682f9487d6cca64fb2f0929 Author: Roger Sayle Date: Fri Jun 10 15:14:23 2022 +0100 PR rtl-optimization/7061: Complex number arguments on x86_64-like ABIs. This patch addresses the issue in comment #6 of PR rtl-optimization/7061 (a four digit PR number) from 2006 where on x86_64 complex number arguments are unconditionally spilled to the stack. For the test cases below: float re(float _Complex a) { return __real__ a; } float im(float _Complex a) { return __imag__ a; } GCC with -O2 currently generates: re: movq %xmm0, -8(%rsp) movss -8(%rsp), %xmm0 ret im: movq %xmm0, -8(%rsp) movss -4(%rsp), %xmm0 ret with this patch we now generate: re: ret im: movq %xmm0, %rax shrq $32, %rax movd %eax, %xmm0 ret [Technically, this shift can be performed on %xmm0 in a single instruction, but the backend needs to be taught to do that, the important bit is that the SCmode argument isn't written to the stack]. The patch itself is to emit_group_store where just before RTL expansion commits to writing to the stack, we check if the store group consists of a single scalar integer register that holds a complex mode value; on x86_64 SCmode arguments are passed in DImode registers. If this is the case, we can use a SUBREG to "view_convert" the integer to the equivalent complex mode. An interesting corner case that showed up during testing is that x86_64 also passes HCmode arguments in DImode registers(!), i.e. using modes of different sizes. This is easily handled/supported by first converting to an integer mode of the correct size, and then generating a complex mode SUBREG of this. This is similar in concept to the patch I proposed here: https://gcc.gnu.org/pipermail/gcc-patches/2022-February/590139.html 2020-06-10 Roger Sayle gcc/ChangeLog PR rtl-optimization/7061 * expr.cc (emit_group_store): For groups that consist of a single scalar integer register that hold a complex mode value, use gen_lowpart to generate a SUBREG to "view_convert" to the complex mode. For modes of different sizes, first convert to an integer mode of the appropriate size. gcc/testsuite/ChangeLog PR rtl-optimization/7061 * gcc.target/i386/pr7061-1.c: New test case. * gcc.target/i386/pr7061-2.c: New test case. Diff: --- gcc/expr.cc | 18 +++++++++++++++++- gcc/testsuite/gcc.target/i386/pr7061-1.c | 4 ++++ gcc/testsuite/gcc.target/i386/pr7061-2.c | 5 +++++ 3 files changed, 26 insertions(+), 1 deletion(-) diff --git a/gcc/expr.cc b/gcc/expr.cc index c37a9990536..78c839ab425 100644 --- a/gcc/expr.cc +++ b/gcc/expr.cc @@ -2801,10 +2801,26 @@ emit_group_store (rtx orig_dst, rtx src, tree type ATTRIBUTE_UNUSED, { machine_mode dest_mode = GET_MODE (dest); machine_mode tmp_mode = GET_MODE (tmps[i]); + scalar_int_mode imode; gcc_assert (known_eq (bytepos, 0) && XVECLEN (src, 0)); - if (GET_MODE_ALIGNMENT (dest_mode) + if (finish == 1 + && REG_P (tmps[i]) + && COMPLEX_MODE_P (dest_mode) + && SCALAR_INT_MODE_P (tmp_mode) + && int_mode_for_mode (dest_mode).exists (&imode)) + { + if (tmp_mode != imode) + { + rtx tmp = gen_reg_rtx (imode); + emit_move_insn (tmp, gen_lowpart (imode, tmps[i])); + dst = gen_lowpart (dest_mode, tmp); + } + else + dst = gen_lowpart (dest_mode, tmps[i]); + } + else if (GET_MODE_ALIGNMENT (dest_mode) >= GET_MODE_ALIGNMENT (tmp_mode)) { dest = assign_stack_temp (dest_mode, diff --git a/gcc/testsuite/gcc.target/i386/pr7061-1.c b/gcc/testsuite/gcc.target/i386/pr7061-1.c new file mode 100644 index 00000000000..ce5f6b2741c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr7061-1.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ +float re(float _Complex a) { return __real__ a; } +/* { dg-final { scan-assembler-not "mov" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr7061-2.c b/gcc/testsuite/gcc.target/i386/pr7061-2.c new file mode 100644 index 00000000000..ac33340099b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr7061-2.c @@ -0,0 +1,5 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ +float im(float _Complex a) { return __imag__ a; } +/* { dg-final { scan-assembler-not "movss" } } */ +/* { dg-final { scan-assembler-not "rsp" } } */