From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1880) id 3C5EC383EC59; Sat, 11 Jun 2022 23:12:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3C5EC383EC59 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Max Filippov To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-1050] xtensa: Tweak some widen multiplications X-Act-Checkin: gcc X-Git-Author: Takayuki 'January June' Suwa X-Git-Refname: refs/heads/master X-Git-Oldrev: fddb7f65129a12dabb5ddc3c8082fe576f4af451 X-Git-Newrev: 9489a1ab05ad1bda7126da5513f08282da3e531d Message-Id: <20220611231206.3C5EC383EC59@sourceware.org> Date: Sat, 11 Jun 2022 23:12:06 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 11 Jun 2022 23:12:06 -0000 https://gcc.gnu.org/g:9489a1ab05ad1bda7126da5513f08282da3e531d commit r13-1050-g9489a1ab05ad1bda7126da5513f08282da3e531d Author: Takayuki 'January June' Suwa Date: Fri Jun 10 13:17:40 2022 +0900 xtensa: Tweak some widen multiplications umulsidi3 is faster than umuldi3 even if library call, and is also prerequisite for fast constant division by multiplication. gcc/ChangeLog: * config/xtensa/xtensa.md (mulsidi3, umulsidi3): Split into individual signedness, in order to use libcall "__umulsidi3" but not the other. (mulhisi3): Merge into one by using code iterator. (mulsidi3, mulhisi3, umulhisi3): Remove. Diff: --- gcc/config/xtensa/xtensa.md | 56 ++++++++++++++++++++++++++------------------- 1 file changed, 32 insertions(+), 24 deletions(-) diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md index 8ff6f9a95fe..33cbd546de3 100644 --- a/gcc/config/xtensa/xtensa.md +++ b/gcc/config/xtensa/xtensa.md @@ -224,20 +224,42 @@ ;; Multiplication. -(define_expand "mulsidi3" +(define_expand "mulsidi3" [(set (match_operand:DI 0 "register_operand") - (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand")) - (any_extend:DI (match_operand:SI 2 "register_operand"))))] + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand")) + (sign_extend:DI (match_operand:SI 2 "register_operand"))))] "TARGET_MUL32_HIGH" { rtx temp = gen_reg_rtx (SImode); emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); - emit_insn (gen_mulsi3_highpart (gen_highpart (SImode, operands[0]), - operands[1], operands[2])); + emit_insn (gen_mulsi3_highpart (gen_highpart (SImode, operands[0]), + operands[1], operands[2])); emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), temp)); DONE; }) +(define_expand "umulsidi3" + [(set (match_operand:DI 0 "register_operand") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand")) + (zero_extend:DI (match_operand:SI 2 "register_operand"))))] + "" +{ + if (TARGET_MUL32_HIGH) + { + rtx temp = gen_reg_rtx (SImode); + emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); + emit_insn (gen_umulsi3_highpart (gen_highpart (SImode, operands[0]), + operands[1], operands[2])); + emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), temp)); + } + else + emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, "__umulsidi3"), + operands[0], LCT_NORMAL, DImode, + operands[1], SImode, + operands[2], SImode); + DONE; +}) + (define_insn "mulsi3_highpart" [(set (match_operand:SI 0 "register_operand" "=a") (truncate:SI @@ -261,30 +283,16 @@ (set_attr "mode" "SI") (set_attr "length" "3")]) -(define_insn "mulhisi3" - [(set (match_operand:SI 0 "register_operand" "=C,A") - (mult:SI (sign_extend:SI - (match_operand:HI 1 "register_operand" "%r,r")) - (sign_extend:SI - (match_operand:HI 2 "register_operand" "r,r"))))] - "TARGET_MUL16 || TARGET_MAC16" - "@ - mul16s\t%0, %1, %2 - mul.aa.ll\t%1, %2" - [(set_attr "type" "mul16,mac16") - (set_attr "mode" "SI") - (set_attr "length" "3,3")]) - -(define_insn "umulhisi3" +(define_insn "mulhisi3" [(set (match_operand:SI 0 "register_operand" "=C,A") - (mult:SI (zero_extend:SI + (mult:SI (any_extend:SI (match_operand:HI 1 "register_operand" "%r,r")) - (zero_extend:SI + (any_extend:SI (match_operand:HI 2 "register_operand" "r,r"))))] "TARGET_MUL16 || TARGET_MAC16" "@ - mul16u\t%0, %1, %2 - umul.aa.ll\t%1, %2" + mul16\t%0, %1, %2 + mul.aa.ll\t%1, %2" [(set_attr "type" "mul16,mac16") (set_attr "mode" "SI") (set_attr "length" "3,3")])